0001 [
0002 {
0003 "BriefDescription": "Number of times HLE abort was triggered",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0xc8",
0007 "EventName": "HLE_RETIRED.ABORTED",
0008 "PEBS": "1",
0009 "PublicDescription": "Number of times HLE abort was triggered.",
0010 "SampleAfterValue": "2000003",
0011 "UMask": "0x4"
0012 },
0013 {
0014 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
0015 "Counter": "0,1,2,3",
0016 "CounterHTOff": "0,1,2,3,4,5,6,7",
0017 "EventCode": "0xc8",
0018 "EventName": "HLE_RETIRED.ABORTED_MISC1",
0019 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
0020 "SampleAfterValue": "2000003",
0021 "UMask": "0x8"
0022 },
0023 {
0024 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
0025 "Counter": "0,1,2,3",
0026 "CounterHTOff": "0,1,2,3,4,5,6,7",
0027 "EventCode": "0xc8",
0028 "EventName": "HLE_RETIRED.ABORTED_MISC2",
0029 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
0030 "SampleAfterValue": "2000003",
0031 "UMask": "0x10"
0032 },
0033 {
0034 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
0035 "Counter": "0,1,2,3",
0036 "CounterHTOff": "0,1,2,3,4,5,6,7",
0037 "EventCode": "0xc8",
0038 "EventName": "HLE_RETIRED.ABORTED_MISC3",
0039 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
0040 "SampleAfterValue": "2000003",
0041 "UMask": "0x20"
0042 },
0043 {
0044 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
0045 "Counter": "0,1,2,3",
0046 "CounterHTOff": "0,1,2,3,4,5,6,7",
0047 "EventCode": "0xc8",
0048 "EventName": "HLE_RETIRED.ABORTED_MISC4",
0049 "PublicDescription": "Number of times HLE caused a fault.",
0050 "SampleAfterValue": "2000003",
0051 "UMask": "0x40"
0052 },
0053 {
0054 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
0055 "Counter": "0,1,2,3",
0056 "CounterHTOff": "0,1,2,3,4,5,6,7",
0057 "EventCode": "0xc8",
0058 "EventName": "HLE_RETIRED.ABORTED_MISC5",
0059 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
0060 "SampleAfterValue": "2000003",
0061 "UMask": "0x80"
0062 },
0063 {
0064 "BriefDescription": "Number of times HLE commit succeeded",
0065 "Counter": "0,1,2,3",
0066 "CounterHTOff": "0,1,2,3,4,5,6,7",
0067 "EventCode": "0xc8",
0068 "EventName": "HLE_RETIRED.COMMIT",
0069 "PublicDescription": "Number of times HLE commit succeeded.",
0070 "SampleAfterValue": "2000003",
0071 "UMask": "0x2"
0072 },
0073 {
0074 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
0075 "Counter": "0,1,2,3",
0076 "CounterHTOff": "0,1,2,3,4,5,6,7",
0077 "EventCode": "0xc8",
0078 "EventName": "HLE_RETIRED.START",
0079 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
0080 "SampleAfterValue": "2000003",
0081 "UMask": "0x1"
0082 },
0083 {
0084 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
0085 "Counter": "0,1,2,3",
0086 "CounterHTOff": "0,1,2,3,4,5,6,7",
0087 "EventCode": "0xC3",
0088 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
0089 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
0090 "SampleAfterValue": "100003",
0091 "UMask": "0x2"
0092 },
0093 {
0094 "BriefDescription": "Randomly selected loads with latency value being above 128",
0095 "Counter": "3",
0096 "CounterHTOff": "3",
0097 "Data_LA": "1",
0098 "Errata": "BDM100, BDM35",
0099 "EventCode": "0xcd",
0100 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
0101 "MSRIndex": "0x3F6",
0102 "MSRValue": "0x80",
0103 "PEBS": "2",
0104 "PublicDescription": "Counts randomly selected loads with latency value being above 128.",
0105 "SampleAfterValue": "1009",
0106 "TakenAlone": "1",
0107 "UMask": "0x1"
0108 },
0109 {
0110 "BriefDescription": "Randomly selected loads with latency value being above 16",
0111 "Counter": "3",
0112 "CounterHTOff": "3",
0113 "Data_LA": "1",
0114 "Errata": "BDM100, BDM35",
0115 "EventCode": "0xcd",
0116 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
0117 "MSRIndex": "0x3F6",
0118 "MSRValue": "0x10",
0119 "PEBS": "2",
0120 "PublicDescription": "Counts randomly selected loads with latency value being above 16.",
0121 "SampleAfterValue": "20011",
0122 "TakenAlone": "1",
0123 "UMask": "0x1"
0124 },
0125 {
0126 "BriefDescription": "Randomly selected loads with latency value being above 256",
0127 "Counter": "3",
0128 "CounterHTOff": "3",
0129 "Data_LA": "1",
0130 "Errata": "BDM100, BDM35",
0131 "EventCode": "0xcd",
0132 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
0133 "MSRIndex": "0x3F6",
0134 "MSRValue": "0x100",
0135 "PEBS": "2",
0136 "PublicDescription": "Counts randomly selected loads with latency value being above 256.",
0137 "SampleAfterValue": "503",
0138 "TakenAlone": "1",
0139 "UMask": "0x1"
0140 },
0141 {
0142 "BriefDescription": "Randomly selected loads with latency value being above 32",
0143 "Counter": "3",
0144 "CounterHTOff": "3",
0145 "Data_LA": "1",
0146 "Errata": "BDM100, BDM35",
0147 "EventCode": "0xcd",
0148 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
0149 "MSRIndex": "0x3F6",
0150 "MSRValue": "0x20",
0151 "PEBS": "2",
0152 "PublicDescription": "Counts randomly selected loads with latency value being above 32.",
0153 "SampleAfterValue": "100007",
0154 "TakenAlone": "1",
0155 "UMask": "0x1"
0156 },
0157 {
0158 "BriefDescription": "Randomly selected loads with latency value being above 4",
0159 "Counter": "3",
0160 "CounterHTOff": "3",
0161 "Data_LA": "1",
0162 "Errata": "BDM100, BDM35",
0163 "EventCode": "0xcd",
0164 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
0165 "MSRIndex": "0x3F6",
0166 "MSRValue": "0x4",
0167 "PEBS": "2",
0168 "PublicDescription": "Counts randomly selected loads with latency value being above four.",
0169 "SampleAfterValue": "100003",
0170 "TakenAlone": "1",
0171 "UMask": "0x1"
0172 },
0173 {
0174 "BriefDescription": "Randomly selected loads with latency value being above 512",
0175 "Counter": "3",
0176 "CounterHTOff": "3",
0177 "Data_LA": "1",
0178 "Errata": "BDM100, BDM35",
0179 "EventCode": "0xcd",
0180 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
0181 "MSRIndex": "0x3F6",
0182 "MSRValue": "0x200",
0183 "PEBS": "2",
0184 "PublicDescription": "Counts randomly selected loads with latency value being above 512.",
0185 "SampleAfterValue": "101",
0186 "TakenAlone": "1",
0187 "UMask": "0x1"
0188 },
0189 {
0190 "BriefDescription": "Randomly selected loads with latency value being above 64",
0191 "Counter": "3",
0192 "CounterHTOff": "3",
0193 "Data_LA": "1",
0194 "Errata": "BDM100, BDM35",
0195 "EventCode": "0xcd",
0196 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
0197 "MSRIndex": "0x3F6",
0198 "MSRValue": "0x40",
0199 "PEBS": "2",
0200 "PublicDescription": "Counts randomly selected loads with latency value being above 64.",
0201 "SampleAfterValue": "2003",
0202 "TakenAlone": "1",
0203 "UMask": "0x1"
0204 },
0205 {
0206 "BriefDescription": "Randomly selected loads with latency value being above 8",
0207 "Counter": "3",
0208 "CounterHTOff": "3",
0209 "Data_LA": "1",
0210 "Errata": "BDM100, BDM35",
0211 "EventCode": "0xcd",
0212 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
0213 "MSRIndex": "0x3F6",
0214 "MSRValue": "0x8",
0215 "PEBS": "2",
0216 "PublicDescription": "Counts randomly selected loads with latency value being above eight.",
0217 "SampleAfterValue": "50021",
0218 "TakenAlone": "1",
0219 "UMask": "0x1"
0220 },
0221 {
0222 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
0223 "Counter": "0,1,2,3",
0224 "CounterHTOff": "0,1,2,3,4,5,6,7",
0225 "EventCode": "0x05",
0226 "EventName": "MISALIGN_MEM_REF.LOADS",
0227 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
0228 "SampleAfterValue": "2000003",
0229 "UMask": "0x1"
0230 },
0231 {
0232 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
0233 "Counter": "0,1,2,3",
0234 "CounterHTOff": "0,1,2,3,4,5,6,7",
0235 "EventCode": "0x05",
0236 "EventName": "MISALIGN_MEM_REF.STORES",
0237 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
0238 "SampleAfterValue": "2000003",
0239 "UMask": "0x2"
0240 },
0241 {
0242 "BriefDescription": "Counts all demand & prefetch code reads miss in the L3",
0243 "Counter": "0,1,2,3",
0244 "CounterHTOff": "0,1,2,3",
0245 "EventCode": "0xB7, 0xBB",
0246 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.ANY_RESPONSE",
0247 "MSRIndex": "0x1a6,0x1a7",
0248 "MSRValue": "0x3FBFC00244",
0249 "Offcore": "1",
0250 "SampleAfterValue": "100003",
0251 "UMask": "0x1"
0252 },
0253 {
0254 "BriefDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
0255 "Counter": "0,1,2,3",
0256 "CounterHTOff": "0,1,2,3",
0257 "EventCode": "0xB7, 0xBB",
0258 "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
0259 "MSRIndex": "0x1a6,0x1a7",
0260 "MSRValue": "0x604000244",
0261 "Offcore": "1",
0262 "SampleAfterValue": "100003",
0263 "UMask": "0x1"
0264 },
0265 {
0266 "BriefDescription": "Counts all demand & prefetch data reads miss in the L3",
0267 "Counter": "0,1,2,3",
0268 "CounterHTOff": "0,1,2,3",
0269 "EventCode": "0xB7, 0xBB",
0270 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.ANY_RESPONSE",
0271 "MSRIndex": "0x1a6,0x1a7",
0272 "MSRValue": "0x3FBFC00091",
0273 "Offcore": "1",
0274 "SampleAfterValue": "100003",
0275 "UMask": "0x1"
0276 },
0277 {
0278 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
0279 "Counter": "0,1,2,3",
0280 "CounterHTOff": "0,1,2,3",
0281 "EventCode": "0xB7, 0xBB",
0282 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
0283 "MSRIndex": "0x1a6,0x1a7",
0284 "MSRValue": "0x604000091",
0285 "Offcore": "1",
0286 "SampleAfterValue": "100003",
0287 "UMask": "0x1"
0288 },
0289 {
0290 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
0291 "Counter": "0,1,2,3",
0292 "CounterHTOff": "0,1,2,3",
0293 "EventCode": "0xB7, 0xBB",
0294 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
0295 "MSRIndex": "0x1a6,0x1a7",
0296 "MSRValue": "0x63BC00091",
0297 "Offcore": "1",
0298 "SampleAfterValue": "100003",
0299 "UMask": "0x1"
0300 },
0301 {
0302 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
0303 "Counter": "0,1,2,3",
0304 "CounterHTOff": "0,1,2,3",
0305 "EventCode": "0xB7, 0xBB",
0306 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HITM",
0307 "MSRIndex": "0x1a6,0x1a7",
0308 "MSRValue": "0x103FC00091",
0309 "Offcore": "1",
0310 "SampleAfterValue": "100003",
0311 "UMask": "0x1"
0312 },
0313 {
0314 "BriefDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
0315 "Counter": "0,1,2,3",
0316 "CounterHTOff": "0,1,2,3",
0317 "EventCode": "0xB7, 0xBB",
0318 "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
0319 "MSRIndex": "0x1a6,0x1a7",
0320 "MSRValue": "0x87FC00091",
0321 "Offcore": "1",
0322 "SampleAfterValue": "100003",
0323 "UMask": "0x1"
0324 },
0325 {
0326 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
0327 "Counter": "0,1,2,3",
0328 "CounterHTOff": "0,1,2,3",
0329 "EventCode": "0xB7, 0xBB",
0330 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.ANY_RESPONSE",
0331 "MSRIndex": "0x1a6,0x1a7",
0332 "MSRValue": "0x3FBFC007F7",
0333 "Offcore": "1",
0334 "SampleAfterValue": "100003",
0335 "UMask": "0x1"
0336 },
0337 {
0338 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
0339 "Counter": "0,1,2,3",
0340 "CounterHTOff": "0,1,2,3",
0341 "EventCode": "0xB7, 0xBB",
0342 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
0343 "MSRIndex": "0x1a6,0x1a7",
0344 "MSRValue": "0x6040007F7",
0345 "Offcore": "1",
0346 "SampleAfterValue": "100003",
0347 "UMask": "0x1"
0348 },
0349 {
0350 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
0351 "Counter": "0,1,2,3",
0352 "CounterHTOff": "0,1,2,3",
0353 "EventCode": "0xB7, 0xBB",
0354 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
0355 "MSRIndex": "0x1a6,0x1a7",
0356 "MSRValue": "0x63BC007F7",
0357 "Offcore": "1",
0358 "SampleAfterValue": "100003",
0359 "UMask": "0x1"
0360 },
0361 {
0362 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
0363 "Counter": "0,1,2,3",
0364 "CounterHTOff": "0,1,2,3",
0365 "EventCode": "0xB7, 0xBB",
0366 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HITM",
0367 "MSRIndex": "0x1a6,0x1a7",
0368 "MSRValue": "0x103FC007F7",
0369 "Offcore": "1",
0370 "SampleAfterValue": "100003",
0371 "UMask": "0x1"
0372 },
0373 {
0374 "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
0375 "Counter": "0,1,2,3",
0376 "CounterHTOff": "0,1,2,3",
0377 "EventCode": "0xB7, 0xBB",
0378 "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
0379 "MSRIndex": "0x1a6,0x1a7",
0380 "MSRValue": "0x87FC007F7",
0381 "Offcore": "1",
0382 "SampleAfterValue": "100003",
0383 "UMask": "0x1"
0384 },
0385 {
0386 "BriefDescription": "Counts all requests miss in the L3",
0387 "Counter": "0,1,2,3",
0388 "CounterHTOff": "0,1,2,3",
0389 "EventCode": "0xB7, 0xBB",
0390 "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_MISS.ANY_RESPONSE",
0391 "MSRIndex": "0x1a6,0x1a7",
0392 "MSRValue": "0x3FBFC08FFF",
0393 "Offcore": "1",
0394 "SampleAfterValue": "100003",
0395 "UMask": "0x1"
0396 },
0397 {
0398 "BriefDescription": "Counts all demand & prefetch RFOs miss in the L3",
0399 "Counter": "0,1,2,3",
0400 "CounterHTOff": "0,1,2,3",
0401 "EventCode": "0xB7, 0xBB",
0402 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.ANY_RESPONSE",
0403 "MSRIndex": "0x1a6,0x1a7",
0404 "MSRValue": "0x3FBFC00122",
0405 "Offcore": "1",
0406 "SampleAfterValue": "100003",
0407 "UMask": "0x1"
0408 },
0409 {
0410 "BriefDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
0411 "Counter": "0,1,2,3",
0412 "CounterHTOff": "0,1,2,3",
0413 "EventCode": "0xB7, 0xBB",
0414 "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
0415 "MSRIndex": "0x1a6,0x1a7",
0416 "MSRValue": "0x604000122",
0417 "Offcore": "1",
0418 "SampleAfterValue": "100003",
0419 "UMask": "0x1"
0420 },
0421 {
0422 "BriefDescription": "Counts all demand data writes (RFOs) miss in the L3",
0423 "Counter": "0,1,2,3",
0424 "CounterHTOff": "0,1,2,3",
0425 "EventCode": "0xB7, 0xBB",
0426 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.ANY_RESPONSE",
0427 "MSRIndex": "0x1a6,0x1a7",
0428 "MSRValue": "0x3FBFC00002",
0429 "Offcore": "1",
0430 "SampleAfterValue": "100003",
0431 "UMask": "0x1"
0432 },
0433 {
0434 "BriefDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
0435 "Counter": "0,1,2,3",
0436 "CounterHTOff": "0,1,2,3",
0437 "EventCode": "0xB7, 0xBB",
0438 "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.REMOTE_HITM",
0439 "MSRIndex": "0x1a6,0x1a7",
0440 "MSRValue": "0x103FC00002",
0441 "Offcore": "1",
0442 "SampleAfterValue": "100003",
0443 "UMask": "0x1"
0444 },
0445 {
0446 "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
0447 "Counter": "0,1,2,3",
0448 "CounterHTOff": "0,1,2,3",
0449 "EventCode": "0xB7, 0xBB",
0450 "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_MISS.ANY_RESPONSE",
0451 "MSRIndex": "0x1a6,0x1a7",
0452 "MSRValue": "0x3FBFC00200",
0453 "Offcore": "1",
0454 "SampleAfterValue": "100003",
0455 "UMask": "0x1"
0456 },
0457 {
0458 "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
0459 "Counter": "0,1,2,3",
0460 "CounterHTOff": "0,1,2,3",
0461 "EventCode": "0xB7, 0xBB",
0462 "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_MISS.ANY_RESPONSE",
0463 "MSRIndex": "0x1a6,0x1a7",
0464 "MSRValue": "0x3FBFC00100",
0465 "Offcore": "1",
0466 "SampleAfterValue": "100003",
0467 "UMask": "0x1"
0468 },
0469 {
0470 "BriefDescription": "Number of times RTM abort was triggered",
0471 "Counter": "0,1,2,3",
0472 "CounterHTOff": "0,1,2,3",
0473 "EventCode": "0xc9",
0474 "EventName": "RTM_RETIRED.ABORTED",
0475 "PEBS": "1",
0476 "PublicDescription": "Number of times RTM abort was triggered .",
0477 "SampleAfterValue": "2000003",
0478 "UMask": "0x4"
0479 },
0480 {
0481 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
0482 "Counter": "0,1,2,3",
0483 "CounterHTOff": "0,1,2,3",
0484 "EventCode": "0xc9",
0485 "EventName": "RTM_RETIRED.ABORTED_MISC1",
0486 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
0487 "SampleAfterValue": "2000003",
0488 "UMask": "0x8"
0489 },
0490 {
0491 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
0492 "Counter": "0,1,2,3",
0493 "CounterHTOff": "0,1,2,3",
0494 "EventCode": "0xc9",
0495 "EventName": "RTM_RETIRED.ABORTED_MISC2",
0496 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
0497 "SampleAfterValue": "2000003",
0498 "UMask": "0x10"
0499 },
0500 {
0501 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
0502 "Counter": "0,1,2,3",
0503 "CounterHTOff": "0,1,2,3",
0504 "EventCode": "0xc9",
0505 "EventName": "RTM_RETIRED.ABORTED_MISC3",
0506 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
0507 "SampleAfterValue": "2000003",
0508 "UMask": "0x20"
0509 },
0510 {
0511 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
0512 "Counter": "0,1,2,3",
0513 "CounterHTOff": "0,1,2,3",
0514 "EventCode": "0xc9",
0515 "EventName": "RTM_RETIRED.ABORTED_MISC4",
0516 "PublicDescription": "Number of times a RTM caused a fault.",
0517 "SampleAfterValue": "2000003",
0518 "UMask": "0x40"
0519 },
0520 {
0521 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
0522 "Counter": "0,1,2,3",
0523 "CounterHTOff": "0,1,2,3",
0524 "EventCode": "0xc9",
0525 "EventName": "RTM_RETIRED.ABORTED_MISC5",
0526 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
0527 "SampleAfterValue": "2000003",
0528 "UMask": "0x80"
0529 },
0530 {
0531 "BriefDescription": "Number of times RTM commit succeeded",
0532 "Counter": "0,1,2,3",
0533 "CounterHTOff": "0,1,2,3",
0534 "EventCode": "0xc9",
0535 "EventName": "RTM_RETIRED.COMMIT",
0536 "PublicDescription": "Number of times RTM commit succeeded.",
0537 "SampleAfterValue": "2000003",
0538 "UMask": "0x2"
0539 },
0540 {
0541 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
0542 "Counter": "0,1,2,3",
0543 "CounterHTOff": "0,1,2,3",
0544 "EventCode": "0xc9",
0545 "EventName": "RTM_RETIRED.START",
0546 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
0547 "SampleAfterValue": "2000003",
0548 "UMask": "0x1"
0549 },
0550 {
0551 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
0552 "Counter": "0,1,2,3",
0553 "CounterHTOff": "0,1,2,3,4,5,6,7",
0554 "EventCode": "0x5d",
0555 "EventName": "TX_EXEC.MISC1",
0556 "SampleAfterValue": "2000003",
0557 "UMask": "0x1"
0558 },
0559 {
0560 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
0561 "Counter": "0,1,2,3",
0562 "CounterHTOff": "0,1,2,3,4,5,6,7",
0563 "EventCode": "0x5d",
0564 "EventName": "TX_EXEC.MISC2",
0565 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
0566 "SampleAfterValue": "2000003",
0567 "UMask": "0x2"
0568 },
0569 {
0570 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
0571 "Counter": "0,1,2,3",
0572 "CounterHTOff": "0,1,2,3,4,5,6,7",
0573 "EventCode": "0x5d",
0574 "EventName": "TX_EXEC.MISC3",
0575 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
0576 "SampleAfterValue": "2000003",
0577 "UMask": "0x4"
0578 },
0579 {
0580 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
0581 "Counter": "0,1,2,3",
0582 "CounterHTOff": "0,1,2,3,4,5,6,7",
0583 "EventCode": "0x5d",
0584 "EventName": "TX_EXEC.MISC4",
0585 "PublicDescription": "RTM region detected inside HLE.",
0586 "SampleAfterValue": "2000003",
0587 "UMask": "0x8"
0588 },
0589 {
0590 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
0591 "Counter": "0,1,2,3",
0592 "CounterHTOff": "0,1,2,3,4,5,6,7",
0593 "EventCode": "0x5d",
0594 "EventName": "TX_EXEC.MISC5",
0595 "SampleAfterValue": "2000003",
0596 "UMask": "0x10"
0597 },
0598 {
0599 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
0600 "Counter": "0,1,2,3",
0601 "CounterHTOff": "0,1,2,3,4,5,6,7",
0602 "EventCode": "0x54",
0603 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
0604 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
0605 "SampleAfterValue": "2000003",
0606 "UMask": "0x2"
0607 },
0608 {
0609 "BriefDescription": "Number of times a TSX line had a cache conflict",
0610 "Counter": "0,1,2,3",
0611 "CounterHTOff": "0,1,2,3,4,5,6,7",
0612 "EventCode": "0x54",
0613 "EventName": "TX_MEM.ABORT_CONFLICT",
0614 "PublicDescription": "Number of times a TSX line had a cache conflict.",
0615 "SampleAfterValue": "2000003",
0616 "UMask": "0x1"
0617 },
0618 {
0619 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
0620 "Counter": "0,1,2,3",
0621 "CounterHTOff": "0,1,2,3,4,5,6,7",
0622 "EventCode": "0x54",
0623 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
0624 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
0625 "SampleAfterValue": "2000003",
0626 "UMask": "0x10"
0627 },
0628 {
0629 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
0630 "Counter": "0,1,2,3",
0631 "CounterHTOff": "0,1,2,3,4,5,6,7",
0632 "EventCode": "0x54",
0633 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
0634 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
0635 "SampleAfterValue": "2000003",
0636 "UMask": "0x8"
0637 },
0638 {
0639 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
0640 "Counter": "0,1,2,3",
0641 "CounterHTOff": "0,1,2,3,4,5,6,7",
0642 "EventCode": "0x54",
0643 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
0644 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
0645 "SampleAfterValue": "2000003",
0646 "UMask": "0x20"
0647 },
0648 {
0649 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
0650 "Counter": "0,1,2,3",
0651 "CounterHTOff": "0,1,2,3,4,5,6,7",
0652 "EventCode": "0x54",
0653 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
0654 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
0655 "SampleAfterValue": "2000003",
0656 "UMask": "0x4"
0657 },
0658 {
0659 "BriefDescription": "Number of times we could not allocate Lock Buffer",
0660 "Counter": "0,1,2,3",
0661 "CounterHTOff": "0,1,2,3,4,5,6,7",
0662 "EventCode": "0x54",
0663 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
0664 "PublicDescription": "Number of times we could not allocate Lock Buffer.",
0665 "SampleAfterValue": "2000003",
0666 "UMask": "0x40"
0667 }
0668 ]
