0001 [
0002 {
0003 "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0x5C",
0007 "EventName": "CPL_CYCLES.RING0",
0008 "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
0009 "SampleAfterValue": "2000003",
0010 "UMask": "0x1"
0011 },
0012 {
0013 "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
0014 "Counter": "0,1,2,3",
0015 "CounterHTOff": "0,1,2,3,4,5,6,7",
0016 "CounterMask": "1",
0017 "EdgeDetect": "1",
0018 "EventCode": "0x5C",
0019 "EventName": "CPL_CYCLES.RING0_TRANS",
0020 "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
0021 "SampleAfterValue": "100007",
0022 "UMask": "0x1"
0023 },
0024 {
0025 "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
0026 "Counter": "0,1,2,3",
0027 "CounterHTOff": "0,1,2,3,4,5,6,7",
0028 "EventCode": "0x5C",
0029 "EventName": "CPL_CYCLES.RING123",
0030 "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
0031 "SampleAfterValue": "2000003",
0032 "UMask": "0x2"
0033 },
0034 {
0035 "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
0036 "Counter": "0,1,2,3",
0037 "CounterHTOff": "0,1,2,3,4,5,6,7",
0038 "EventCode": "0x63",
0039 "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
0040 "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
0041 "SampleAfterValue": "2000003",
0042 "UMask": "0x1"
0043 }
0044 ]
