0001 [
0002 {
0003 "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
0004 "Counter": "0,1,2,3",
0005 "CounterHTOff": "0,1,2,3,4,5,6,7",
0006 "EventCode": "0xc8",
0007 "EventName": "HLE_RETIRED.ABORTED",
0008 "PEBS": "1",
0009 "PublicDescription": "Number of times HLE abort was triggered (PEBS).",
0010 "SampleAfterValue": "2000003",
0011 "UMask": "0x4"
0012 },
0013 {
0014 "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
0015 "Counter": "0,1,2,3",
0016 "CounterHTOff": "0,1,2,3,4,5,6,7",
0017 "EventCode": "0xc8",
0018 "EventName": "HLE_RETIRED.ABORTED_MISC1",
0019 "PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
0020 "SampleAfterValue": "2000003",
0021 "UMask": "0x8"
0022 },
0023 {
0024 "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
0025 "Counter": "0,1,2,3",
0026 "CounterHTOff": "0,1,2,3,4,5,6,7",
0027 "EventCode": "0xc8",
0028 "EventName": "HLE_RETIRED.ABORTED_MISC2",
0029 "PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
0030 "SampleAfterValue": "2000003",
0031 "UMask": "0x10"
0032 },
0033 {
0034 "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
0035 "Counter": "0,1,2,3",
0036 "CounterHTOff": "0,1,2,3,4,5,6,7",
0037 "EventCode": "0xc8",
0038 "EventName": "HLE_RETIRED.ABORTED_MISC3",
0039 "PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
0040 "SampleAfterValue": "2000003",
0041 "UMask": "0x20"
0042 },
0043 {
0044 "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
0045 "Counter": "0,1,2,3",
0046 "CounterHTOff": "0,1,2,3,4,5,6,7",
0047 "EventCode": "0xc8",
0048 "EventName": "HLE_RETIRED.ABORTED_MISC4",
0049 "PublicDescription": "Number of times HLE caused a fault.",
0050 "SampleAfterValue": "2000003",
0051 "UMask": "0x40"
0052 },
0053 {
0054 "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
0055 "Counter": "0,1,2,3",
0056 "CounterHTOff": "0,1,2,3,4,5,6,7",
0057 "EventCode": "0xc8",
0058 "EventName": "HLE_RETIRED.ABORTED_MISC5",
0059 "PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
0060 "SampleAfterValue": "2000003",
0061 "UMask": "0x80"
0062 },
0063 {
0064 "BriefDescription": "Number of times HLE commit succeeded",
0065 "Counter": "0,1,2,3",
0066 "CounterHTOff": "0,1,2,3,4,5,6,7",
0067 "EventCode": "0xc8",
0068 "EventName": "HLE_RETIRED.COMMIT",
0069 "PublicDescription": "Number of times HLE commit succeeded.",
0070 "SampleAfterValue": "2000003",
0071 "UMask": "0x2"
0072 },
0073 {
0074 "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
0075 "Counter": "0,1,2,3",
0076 "CounterHTOff": "0,1,2,3,4,5,6,7",
0077 "EventCode": "0xc8",
0078 "EventName": "HLE_RETIRED.START",
0079 "PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
0080 "SampleAfterValue": "2000003",
0081 "UMask": "0x1"
0082 },
0083 {
0084 "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
0085 "Counter": "0,1,2,3",
0086 "CounterHTOff": "0,1,2,3,4,5,6,7",
0087 "EventCode": "0xC3",
0088 "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
0089 "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
0090 "SampleAfterValue": "100003",
0091 "UMask": "0x2"
0092 },
0093 {
0094 "BriefDescription": "Loads with latency value being above 128",
0095 "Counter": "3",
0096 "CounterHTOff": "3",
0097 "Errata": "BDM100, BDM35",
0098 "EventCode": "0xCD",
0099 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
0100 "MSRIndex": "0x3F6",
0101 "MSRValue": "0x80",
0102 "PEBS": "2",
0103 "PublicDescription": "This event counts loads with latency value being above 128.",
0104 "SampleAfterValue": "1009",
0105 "TakenAlone": "1",
0106 "UMask": "0x1"
0107 },
0108 {
0109 "BriefDescription": "Loads with latency value being above 16",
0110 "Counter": "3",
0111 "CounterHTOff": "3",
0112 "Errata": "BDM100, BDM35",
0113 "EventCode": "0xCD",
0114 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
0115 "MSRIndex": "0x3F6",
0116 "MSRValue": "0x10",
0117 "PEBS": "2",
0118 "PublicDescription": "This event counts loads with latency value being above 16.",
0119 "SampleAfterValue": "20011",
0120 "TakenAlone": "1",
0121 "UMask": "0x1"
0122 },
0123 {
0124 "BriefDescription": "Loads with latency value being above 256",
0125 "Counter": "3",
0126 "CounterHTOff": "3",
0127 "Errata": "BDM100, BDM35",
0128 "EventCode": "0xCD",
0129 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
0130 "MSRIndex": "0x3F6",
0131 "MSRValue": "0x100",
0132 "PEBS": "2",
0133 "PublicDescription": "This event counts loads with latency value being above 256.",
0134 "SampleAfterValue": "503",
0135 "TakenAlone": "1",
0136 "UMask": "0x1"
0137 },
0138 {
0139 "BriefDescription": "Loads with latency value being above 32",
0140 "Counter": "3",
0141 "CounterHTOff": "3",
0142 "Errata": "BDM100, BDM35",
0143 "EventCode": "0xCD",
0144 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
0145 "MSRIndex": "0x3F6",
0146 "MSRValue": "0x20",
0147 "PEBS": "2",
0148 "PublicDescription": "This event counts loads with latency value being above 32.",
0149 "SampleAfterValue": "100007",
0150 "TakenAlone": "1",
0151 "UMask": "0x1"
0152 },
0153 {
0154 "BriefDescription": "Loads with latency value being above 4",
0155 "Counter": "3",
0156 "CounterHTOff": "3",
0157 "Errata": "BDM100, BDM35",
0158 "EventCode": "0xCD",
0159 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
0160 "MSRIndex": "0x3F6",
0161 "MSRValue": "0x4",
0162 "PEBS": "2",
0163 "PublicDescription": "This event counts loads with latency value being above four.",
0164 "SampleAfterValue": "100003",
0165 "TakenAlone": "1",
0166 "UMask": "0x1"
0167 },
0168 {
0169 "BriefDescription": "Loads with latency value being above 512",
0170 "Counter": "3",
0171 "CounterHTOff": "3",
0172 "Errata": "BDM100, BDM35",
0173 "EventCode": "0xCD",
0174 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
0175 "MSRIndex": "0x3F6",
0176 "MSRValue": "0x200",
0177 "PEBS": "2",
0178 "PublicDescription": "This event counts loads with latency value being above 512.",
0179 "SampleAfterValue": "101",
0180 "TakenAlone": "1",
0181 "UMask": "0x1"
0182 },
0183 {
0184 "BriefDescription": "Loads with latency value being above 64",
0185 "Counter": "3",
0186 "CounterHTOff": "3",
0187 "Errata": "BDM100, BDM35",
0188 "EventCode": "0xCD",
0189 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
0190 "MSRIndex": "0x3F6",
0191 "MSRValue": "0x40",
0192 "PEBS": "2",
0193 "PublicDescription": "This event counts loads with latency value being above 64.",
0194 "SampleAfterValue": "2003",
0195 "TakenAlone": "1",
0196 "UMask": "0x1"
0197 },
0198 {
0199 "BriefDescription": "Loads with latency value being above 8",
0200 "Counter": "3",
0201 "CounterHTOff": "3",
0202 "Errata": "BDM100, BDM35",
0203 "EventCode": "0xCD",
0204 "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
0205 "MSRIndex": "0x3F6",
0206 "MSRValue": "0x8",
0207 "PEBS": "2",
0208 "PublicDescription": "This event counts loads with latency value being above eight.",
0209 "SampleAfterValue": "50021",
0210 "TakenAlone": "1",
0211 "UMask": "0x1"
0212 },
0213 {
0214 "BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
0215 "Counter": "0,1,2,3",
0216 "CounterHTOff": "0,1,2,3,4,5,6,7",
0217 "EventCode": "0x05",
0218 "EventName": "MISALIGN_MEM_REF.LOADS",
0219 "PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
0220 "SampleAfterValue": "2000003",
0221 "UMask": "0x1"
0222 },
0223 {
0224 "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
0225 "Counter": "0,1,2,3",
0226 "CounterHTOff": "0,1,2,3,4,5,6,7",
0227 "EventCode": "0x05",
0228 "EventName": "MISALIGN_MEM_REF.STORES",
0229 "PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
0230 "SampleAfterValue": "2000003",
0231 "UMask": "0x2"
0232 },
0233 {
0234 "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
0235 "Counter": "0,1,2,3",
0236 "CounterHTOff": "0,1,2,3",
0237 "EventCode": "0xc9",
0238 "EventName": "RTM_RETIRED.ABORTED",
0239 "PEBS": "1",
0240 "PublicDescription": "Number of times RTM abort was triggered (PEBS).",
0241 "SampleAfterValue": "2000003",
0242 "UMask": "0x4"
0243 },
0244 {
0245 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
0246 "Counter": "0,1,2,3",
0247 "CounterHTOff": "0,1,2,3",
0248 "EventCode": "0xc9",
0249 "EventName": "RTM_RETIRED.ABORTED_MISC1",
0250 "PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
0251 "SampleAfterValue": "2000003",
0252 "UMask": "0x8"
0253 },
0254 {
0255 "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
0256 "Counter": "0,1,2,3",
0257 "CounterHTOff": "0,1,2,3",
0258 "EventCode": "0xc9",
0259 "EventName": "RTM_RETIRED.ABORTED_MISC2",
0260 "PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
0261 "SampleAfterValue": "2000003",
0262 "UMask": "0x10"
0263 },
0264 {
0265 "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
0266 "Counter": "0,1,2,3",
0267 "CounterHTOff": "0,1,2,3",
0268 "EventCode": "0xc9",
0269 "EventName": "RTM_RETIRED.ABORTED_MISC3",
0270 "PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
0271 "SampleAfterValue": "2000003",
0272 "UMask": "0x20"
0273 },
0274 {
0275 "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
0276 "Counter": "0,1,2,3",
0277 "CounterHTOff": "0,1,2,3",
0278 "EventCode": "0xc9",
0279 "EventName": "RTM_RETIRED.ABORTED_MISC4",
0280 "PublicDescription": "Number of times a RTM caused a fault.",
0281 "SampleAfterValue": "2000003",
0282 "UMask": "0x40"
0283 },
0284 {
0285 "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
0286 "Counter": "0,1,2,3",
0287 "CounterHTOff": "0,1,2,3",
0288 "EventCode": "0xc9",
0289 "EventName": "RTM_RETIRED.ABORTED_MISC5",
0290 "PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
0291 "SampleAfterValue": "2000003",
0292 "UMask": "0x80"
0293 },
0294 {
0295 "BriefDescription": "Number of times RTM commit succeeded",
0296 "Counter": "0,1,2,3",
0297 "CounterHTOff": "0,1,2,3",
0298 "EventCode": "0xc9",
0299 "EventName": "RTM_RETIRED.COMMIT",
0300 "PublicDescription": "Number of times RTM commit succeeded.",
0301 "SampleAfterValue": "2000003",
0302 "UMask": "0x2"
0303 },
0304 {
0305 "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
0306 "Counter": "0,1,2,3",
0307 "CounterHTOff": "0,1,2,3",
0308 "EventCode": "0xc9",
0309 "EventName": "RTM_RETIRED.START",
0310 "PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
0311 "SampleAfterValue": "2000003",
0312 "UMask": "0x1"
0313 },
0314 {
0315 "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
0316 "Counter": "0,1,2,3",
0317 "CounterHTOff": "0,1,2,3,4,5,6,7",
0318 "EventCode": "0x5d",
0319 "EventName": "TX_EXEC.MISC1",
0320 "SampleAfterValue": "2000003",
0321 "UMask": "0x1"
0322 },
0323 {
0324 "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
0325 "Counter": "0,1,2,3",
0326 "CounterHTOff": "0,1,2,3,4,5,6,7",
0327 "EventCode": "0x5d",
0328 "EventName": "TX_EXEC.MISC2",
0329 "PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
0330 "SampleAfterValue": "2000003",
0331 "UMask": "0x2"
0332 },
0333 {
0334 "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
0335 "Counter": "0,1,2,3",
0336 "CounterHTOff": "0,1,2,3,4,5,6,7",
0337 "EventCode": "0x5d",
0338 "EventName": "TX_EXEC.MISC3",
0339 "PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
0340 "SampleAfterValue": "2000003",
0341 "UMask": "0x4"
0342 },
0343 {
0344 "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
0345 "Counter": "0,1,2,3",
0346 "CounterHTOff": "0,1,2,3,4,5,6,7",
0347 "EventCode": "0x5d",
0348 "EventName": "TX_EXEC.MISC4",
0349 "PublicDescription": "RTM region detected inside HLE.",
0350 "SampleAfterValue": "2000003",
0351 "UMask": "0x8"
0352 },
0353 {
0354 "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
0355 "Counter": "0,1,2,3",
0356 "CounterHTOff": "0,1,2,3,4,5,6,7",
0357 "EventCode": "0x5d",
0358 "EventName": "TX_EXEC.MISC5",
0359 "SampleAfterValue": "2000003",
0360 "UMask": "0x10"
0361 },
0362 {
0363 "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
0364 "Counter": "0,1,2,3",
0365 "CounterHTOff": "0,1,2,3,4,5,6,7",
0366 "EventCode": "0x54",
0367 "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
0368 "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
0369 "SampleAfterValue": "2000003",
0370 "UMask": "0x2"
0371 },
0372 {
0373 "BriefDescription": "Number of times a TSX line had a cache conflict",
0374 "Counter": "0,1,2,3",
0375 "CounterHTOff": "0,1,2,3,4,5,6,7",
0376 "EventCode": "0x54",
0377 "EventName": "TX_MEM.ABORT_CONFLICT",
0378 "PublicDescription": "Number of times a TSX line had a cache conflict.",
0379 "SampleAfterValue": "2000003",
0380 "UMask": "0x1"
0381 },
0382 {
0383 "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
0384 "Counter": "0,1,2,3",
0385 "CounterHTOff": "0,1,2,3,4,5,6,7",
0386 "EventCode": "0x54",
0387 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
0388 "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
0389 "SampleAfterValue": "2000003",
0390 "UMask": "0x10"
0391 },
0392 {
0393 "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
0394 "Counter": "0,1,2,3",
0395 "CounterHTOff": "0,1,2,3,4,5,6,7",
0396 "EventCode": "0x54",
0397 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
0398 "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
0399 "SampleAfterValue": "2000003",
0400 "UMask": "0x8"
0401 },
0402 {
0403 "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
0404 "Counter": "0,1,2,3",
0405 "CounterHTOff": "0,1,2,3,4,5,6,7",
0406 "EventCode": "0x54",
0407 "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
0408 "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
0409 "SampleAfterValue": "2000003",
0410 "UMask": "0x20"
0411 },
0412 {
0413 "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
0414 "Counter": "0,1,2,3",
0415 "CounterHTOff": "0,1,2,3,4,5,6,7",
0416 "EventCode": "0x54",
0417 "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
0418 "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
0419 "SampleAfterValue": "2000003",
0420 "UMask": "0x4"
0421 },
0422 {
0423 "BriefDescription": "Number of times we could not allocate Lock Buffer",
0424 "Counter": "0,1,2,3",
0425 "CounterHTOff": "0,1,2,3,4,5,6,7",
0426 "EventCode": "0x54",
0427 "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
0428 "PublicDescription": "Number of times we could not allocate Lock Buffer.",
0429 "SampleAfterValue": "2000003",
0430 "UMask": "0x40"
0431 }
0432 ]
