0001 [
0002 {
0003 "BriefDescription": "Memory accesses that missed the DTLB.",
0004 "Counter": "0,1",
0005 "EventCode": "0x8",
0006 "EventName": "DATA_TLB_MISSES.DTLB_MISS",
0007 "SampleAfterValue": "200000",
0008 "UMask": "0x7"
0009 },
0010 {
0011 "BriefDescription": "DTLB misses due to load operations.",
0012 "Counter": "0,1",
0013 "EventCode": "0x8",
0014 "EventName": "DATA_TLB_MISSES.DTLB_MISS_LD",
0015 "SampleAfterValue": "200000",
0016 "UMask": "0x5"
0017 },
0018 {
0019 "BriefDescription": "DTLB misses due to store operations.",
0020 "Counter": "0,1",
0021 "EventCode": "0x8",
0022 "EventName": "DATA_TLB_MISSES.DTLB_MISS_ST",
0023 "SampleAfterValue": "200000",
0024 "UMask": "0x6"
0025 },
0026 {
0027 "BriefDescription": "L0 DTLB misses due to load operations.",
0028 "Counter": "0,1",
0029 "EventCode": "0x8",
0030 "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_LD",
0031 "SampleAfterValue": "200000",
0032 "UMask": "0x9"
0033 },
0034 {
0035 "BriefDescription": "L0 DTLB misses due to store operations",
0036 "Counter": "0,1",
0037 "EventCode": "0x8",
0038 "EventName": "DATA_TLB_MISSES.L0_DTLB_MISS_ST",
0039 "SampleAfterValue": "200000",
0040 "UMask": "0xa"
0041 },
0042 {
0043 "BriefDescription": "ITLB flushes.",
0044 "Counter": "0,1",
0045 "EventCode": "0x82",
0046 "EventName": "ITLB.FLUSH",
0047 "SampleAfterValue": "200000",
0048 "UMask": "0x4"
0049 },
0050 {
0051 "BriefDescription": "ITLB hits.",
0052 "Counter": "0,1",
0053 "EventCode": "0x82",
0054 "EventName": "ITLB.HIT",
0055 "SampleAfterValue": "200000",
0056 "UMask": "0x1"
0057 },
0058 {
0059 "BriefDescription": "ITLB misses.",
0060 "Counter": "0,1",
0061 "EventCode": "0x82",
0062 "EventName": "ITLB.MISSES",
0063 "PEBS": "2",
0064 "SampleAfterValue": "200000",
0065 "UMask": "0x2"
0066 },
0067 {
0068 "BriefDescription": "Retired loads that miss the DTLB (precise event).",
0069 "Counter": "0,1",
0070 "EventCode": "0xCB",
0071 "EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
0072 "PEBS": "1",
0073 "SampleAfterValue": "200000",
0074 "UMask": "0x4"
0075 },
0076 {
0077 "BriefDescription": "Duration of page-walks in core cycles",
0078 "Counter": "0,1",
0079 "EventCode": "0xC",
0080 "EventName": "PAGE_WALKS.CYCLES",
0081 "SampleAfterValue": "2000000",
0082 "UMask": "0x3"
0083 },
0084 {
0085 "BriefDescription": "Duration of D-side only page walks",
0086 "Counter": "0,1",
0087 "EventCode": "0xC",
0088 "EventName": "PAGE_WALKS.D_SIDE_CYCLES",
0089 "SampleAfterValue": "2000000",
0090 "UMask": "0x1"
0091 },
0092 {
0093 "BriefDescription": "Number of D-side only page walks",
0094 "Counter": "0,1",
0095 "EventCode": "0xC",
0096 "EventName": "PAGE_WALKS.D_SIDE_WALKS",
0097 "SampleAfterValue": "200000",
0098 "UMask": "0x1"
0099 },
0100 {
0101 "BriefDescription": "Duration of I-Side page walks",
0102 "Counter": "0,1",
0103 "EventCode": "0xC",
0104 "EventName": "PAGE_WALKS.I_SIDE_CYCLES",
0105 "SampleAfterValue": "2000000",
0106 "UMask": "0x2"
0107 },
0108 {
0109 "BriefDescription": "Number of I-Side page walks",
0110 "Counter": "0,1",
0111 "EventCode": "0xC",
0112 "EventName": "PAGE_WALKS.I_SIDE_WALKS",
0113 "SampleAfterValue": "200000",
0114 "UMask": "0x2"
0115 },
0116 {
0117 "BriefDescription": "Number of page-walks executed.",
0118 "Counter": "0,1",
0119 "EventCode": "0xC",
0120 "EventName": "PAGE_WALKS.WALKS",
0121 "SampleAfterValue": "200000",
0122 "UMask": "0x3"
0123 }
0124 ]
