0001 [
0002 {
0003 "BriefDescription": "Nonzero segbase 1 bubble",
0004 "Counter": "0,1",
0005 "EventCode": "0x5",
0006 "EventName": "MISALIGN_MEM_REF.BUBBLE",
0007 "SampleAfterValue": "200000",
0008 "UMask": "0x97"
0009 },
0010 {
0011 "BriefDescription": "Nonzero segbase load 1 bubble",
0012 "Counter": "0,1",
0013 "EventCode": "0x5",
0014 "EventName": "MISALIGN_MEM_REF.LD_BUBBLE",
0015 "SampleAfterValue": "200000",
0016 "UMask": "0x91"
0017 },
0018 {
0019 "BriefDescription": "Load splits",
0020 "Counter": "0,1",
0021 "EventCode": "0x5",
0022 "EventName": "MISALIGN_MEM_REF.LD_SPLIT",
0023 "SampleAfterValue": "200000",
0024 "UMask": "0x9"
0025 },
0026 {
0027 "BriefDescription": "Load splits (At Retirement)",
0028 "Counter": "0,1",
0029 "EventCode": "0x5",
0030 "EventName": "MISALIGN_MEM_REF.LD_SPLIT.AR",
0031 "SampleAfterValue": "200000",
0032 "UMask": "0x89"
0033 },
0034 {
0035 "BriefDescription": "Nonzero segbase ld-op-st 1 bubble",
0036 "Counter": "0,1",
0037 "EventCode": "0x5",
0038 "EventName": "MISALIGN_MEM_REF.RMW_BUBBLE",
0039 "SampleAfterValue": "200000",
0040 "UMask": "0x94"
0041 },
0042 {
0043 "BriefDescription": "ld-op-st splits",
0044 "Counter": "0,1",
0045 "EventCode": "0x5",
0046 "EventName": "MISALIGN_MEM_REF.RMW_SPLIT",
0047 "SampleAfterValue": "200000",
0048 "UMask": "0x8c"
0049 },
0050 {
0051 "BriefDescription": "Memory references that cross an 8-byte boundary.",
0052 "Counter": "0,1",
0053 "EventCode": "0x5",
0054 "EventName": "MISALIGN_MEM_REF.SPLIT",
0055 "SampleAfterValue": "200000",
0056 "UMask": "0xf"
0057 },
0058 {
0059 "BriefDescription": "Memory references that cross an 8-byte boundary (At Retirement)",
0060 "Counter": "0,1",
0061 "EventCode": "0x5",
0062 "EventName": "MISALIGN_MEM_REF.SPLIT.AR",
0063 "SampleAfterValue": "200000",
0064 "UMask": "0x8f"
0065 },
0066 {
0067 "BriefDescription": "Nonzero segbase store 1 bubble",
0068 "Counter": "0,1",
0069 "EventCode": "0x5",
0070 "EventName": "MISALIGN_MEM_REF.ST_BUBBLE",
0071 "SampleAfterValue": "200000",
0072 "UMask": "0x92"
0073 },
0074 {
0075 "BriefDescription": "Store splits",
0076 "Counter": "0,1",
0077 "EventCode": "0x5",
0078 "EventName": "MISALIGN_MEM_REF.ST_SPLIT",
0079 "SampleAfterValue": "200000",
0080 "UMask": "0xa"
0081 },
0082 {
0083 "BriefDescription": "Store splits (Ar Retirement)",
0084 "Counter": "0,1",
0085 "EventCode": "0x5",
0086 "EventName": "MISALIGN_MEM_REF.ST_SPLIT.AR",
0087 "SampleAfterValue": "200000",
0088 "UMask": "0x8a"
0089 },
0090 {
0091 "BriefDescription": "L1 hardware prefetch request",
0092 "Counter": "0,1",
0093 "EventCode": "0x7",
0094 "EventName": "PREFETCH.HW_PREFETCH",
0095 "SampleAfterValue": "2000000",
0096 "UMask": "0x10"
0097 },
0098 {
0099 "BriefDescription": "Streaming SIMD Extensions (SSE) Prefetch NTA instructions executed",
0100 "Counter": "0,1",
0101 "EventCode": "0x7",
0102 "EventName": "PREFETCH.PREFETCHNTA",
0103 "SampleAfterValue": "200000",
0104 "UMask": "0x88"
0105 },
0106 {
0107 "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT0 instructions executed.",
0108 "Counter": "0,1",
0109 "EventCode": "0x7",
0110 "EventName": "PREFETCH.PREFETCHT0",
0111 "SampleAfterValue": "200000",
0112 "UMask": "0x81"
0113 },
0114 {
0115 "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 instructions executed.",
0116 "Counter": "0,1",
0117 "EventCode": "0x7",
0118 "EventName": "PREFETCH.PREFETCHT1",
0119 "SampleAfterValue": "200000",
0120 "UMask": "0x82"
0121 },
0122 {
0123 "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT2 instructions executed.",
0124 "Counter": "0,1",
0125 "EventCode": "0x7",
0126 "EventName": "PREFETCH.PREFETCHT2",
0127 "SampleAfterValue": "200000",
0128 "UMask": "0x84"
0129 },
0130 {
0131 "BriefDescription": "Any Software prefetch",
0132 "Counter": "0,1",
0133 "EventCode": "0x7",
0134 "EventName": "PREFETCH.SOFTWARE_PREFETCH",
0135 "SampleAfterValue": "200000",
0136 "UMask": "0xf"
0137 },
0138 {
0139 "BriefDescription": "Any Software prefetch",
0140 "Counter": "0,1",
0141 "EventCode": "0x7",
0142 "EventName": "PREFETCH.SOFTWARE_PREFETCH.AR",
0143 "SampleAfterValue": "200000",
0144 "UMask": "0x8f"
0145 },
0146 {
0147 "BriefDescription": "Streaming SIMD Extensions (SSE) PrefetchT1 and PrefetchT2 instructions executed",
0148 "Counter": "0,1",
0149 "EventCode": "0x7",
0150 "EventName": "PREFETCH.SW_L2",
0151 "SampleAfterValue": "200000",
0152 "UMask": "0x86"
0153 }
0154 ]
