0001 [
0002 {
0003 "BriefDescription": "L1 Data Cacheable reads and writes",
0004 "Counter": "0,1",
0005 "EventCode": "0x40",
0006 "EventName": "L1D_CACHE.ALL_CACHE_REF",
0007 "SampleAfterValue": "2000000",
0008 "UMask": "0xa3"
0009 },
0010 {
0011 "BriefDescription": "L1 Data reads and writes",
0012 "Counter": "0,1",
0013 "EventCode": "0x40",
0014 "EventName": "L1D_CACHE.ALL_REF",
0015 "SampleAfterValue": "2000000",
0016 "UMask": "0x83"
0017 },
0018 {
0019 "BriefDescription": "Modified cache lines evicted from the L1 data cache",
0020 "Counter": "0,1",
0021 "EventCode": "0x40",
0022 "EventName": "L1D_CACHE.EVICT",
0023 "SampleAfterValue": "200000",
0024 "UMask": "0x10"
0025 },
0026 {
0027 "BriefDescription": "L1 Cacheable Data Reads",
0028 "Counter": "0,1",
0029 "EventCode": "0x40",
0030 "EventName": "L1D_CACHE.LD",
0031 "SampleAfterValue": "2000000",
0032 "UMask": "0xa1"
0033 },
0034 {
0035 "BriefDescription": "L1 Data line replacements",
0036 "Counter": "0,1",
0037 "EventCode": "0x40",
0038 "EventName": "L1D_CACHE.REPL",
0039 "SampleAfterValue": "200000",
0040 "UMask": "0x8"
0041 },
0042 {
0043 "BriefDescription": "Modified cache lines allocated in the L1 data cache",
0044 "Counter": "0,1",
0045 "EventCode": "0x40",
0046 "EventName": "L1D_CACHE.REPLM",
0047 "SampleAfterValue": "200000",
0048 "UMask": "0x48"
0049 },
0050 {
0051 "BriefDescription": "L1 Cacheable Data Writes",
0052 "Counter": "0,1",
0053 "EventCode": "0x40",
0054 "EventName": "L1D_CACHE.ST",
0055 "SampleAfterValue": "2000000",
0056 "UMask": "0xa2"
0057 },
0058 {
0059 "BriefDescription": "Cycles L2 address bus is in use.",
0060 "Counter": "0,1",
0061 "EventCode": "0x21",
0062 "EventName": "L2_ADS.SELF",
0063 "SampleAfterValue": "200000",
0064 "UMask": "0x40"
0065 },
0066 {
0067 "BriefDescription": "All data requests from the L1 data cache",
0068 "Counter": "0,1",
0069 "EventCode": "0x2C",
0070 "EventName": "L2_DATA_RQSTS.SELF.E_STATE",
0071 "SampleAfterValue": "200000",
0072 "UMask": "0x44"
0073 },
0074 {
0075 "BriefDescription": "All data requests from the L1 data cache",
0076 "Counter": "0,1",
0077 "EventCode": "0x2C",
0078 "EventName": "L2_DATA_RQSTS.SELF.I_STATE",
0079 "SampleAfterValue": "200000",
0080 "UMask": "0x41"
0081 },
0082 {
0083 "BriefDescription": "All data requests from the L1 data cache",
0084 "Counter": "0,1",
0085 "EventCode": "0x2C",
0086 "EventName": "L2_DATA_RQSTS.SELF.MESI",
0087 "SampleAfterValue": "200000",
0088 "UMask": "0x4f"
0089 },
0090 {
0091 "BriefDescription": "All data requests from the L1 data cache",
0092 "Counter": "0,1",
0093 "EventCode": "0x2C",
0094 "EventName": "L2_DATA_RQSTS.SELF.M_STATE",
0095 "SampleAfterValue": "200000",
0096 "UMask": "0x48"
0097 },
0098 {
0099 "BriefDescription": "All data requests from the L1 data cache",
0100 "Counter": "0,1",
0101 "EventCode": "0x2C",
0102 "EventName": "L2_DATA_RQSTS.SELF.S_STATE",
0103 "SampleAfterValue": "200000",
0104 "UMask": "0x42"
0105 },
0106 {
0107 "BriefDescription": "Cycles the L2 cache data bus is busy.",
0108 "Counter": "0,1",
0109 "EventCode": "0x22",
0110 "EventName": "L2_DBUS_BUSY.SELF",
0111 "SampleAfterValue": "200000",
0112 "UMask": "0x40"
0113 },
0114 {
0115 "BriefDescription": "Cycles the L2 transfers data to the core.",
0116 "Counter": "0,1",
0117 "EventCode": "0x23",
0118 "EventName": "L2_DBUS_BUSY_RD.SELF",
0119 "SampleAfterValue": "200000",
0120 "UMask": "0x40"
0121 },
0122 {
0123 "BriefDescription": "L2 cacheable instruction fetch requests",
0124 "Counter": "0,1",
0125 "EventCode": "0x28",
0126 "EventName": "L2_IFETCH.SELF.E_STATE",
0127 "SampleAfterValue": "200000",
0128 "UMask": "0x44"
0129 },
0130 {
0131 "BriefDescription": "L2 cacheable instruction fetch requests",
0132 "Counter": "0,1",
0133 "EventCode": "0x28",
0134 "EventName": "L2_IFETCH.SELF.I_STATE",
0135 "SampleAfterValue": "200000",
0136 "UMask": "0x41"
0137 },
0138 {
0139 "BriefDescription": "L2 cacheable instruction fetch requests",
0140 "Counter": "0,1",
0141 "EventCode": "0x28",
0142 "EventName": "L2_IFETCH.SELF.MESI",
0143 "SampleAfterValue": "200000",
0144 "UMask": "0x4f"
0145 },
0146 {
0147 "BriefDescription": "L2 cacheable instruction fetch requests",
0148 "Counter": "0,1",
0149 "EventCode": "0x28",
0150 "EventName": "L2_IFETCH.SELF.M_STATE",
0151 "SampleAfterValue": "200000",
0152 "UMask": "0x48"
0153 },
0154 {
0155 "BriefDescription": "L2 cacheable instruction fetch requests",
0156 "Counter": "0,1",
0157 "EventCode": "0x28",
0158 "EventName": "L2_IFETCH.SELF.S_STATE",
0159 "SampleAfterValue": "200000",
0160 "UMask": "0x42"
0161 },
0162 {
0163 "BriefDescription": "L2 cache reads",
0164 "Counter": "0,1",
0165 "EventCode": "0x29",
0166 "EventName": "L2_LD.SELF.ANY.E_STATE",
0167 "SampleAfterValue": "200000",
0168 "UMask": "0x74"
0169 },
0170 {
0171 "BriefDescription": "L2 cache reads",
0172 "Counter": "0,1",
0173 "EventCode": "0x29",
0174 "EventName": "L2_LD.SELF.ANY.I_STATE",
0175 "SampleAfterValue": "200000",
0176 "UMask": "0x71"
0177 },
0178 {
0179 "BriefDescription": "L2 cache reads",
0180 "Counter": "0,1",
0181 "EventCode": "0x29",
0182 "EventName": "L2_LD.SELF.ANY.MESI",
0183 "SampleAfterValue": "200000",
0184 "UMask": "0x7f"
0185 },
0186 {
0187 "BriefDescription": "L2 cache reads",
0188 "Counter": "0,1",
0189 "EventCode": "0x29",
0190 "EventName": "L2_LD.SELF.ANY.M_STATE",
0191 "SampleAfterValue": "200000",
0192 "UMask": "0x78"
0193 },
0194 {
0195 "BriefDescription": "L2 cache reads",
0196 "Counter": "0,1",
0197 "EventCode": "0x29",
0198 "EventName": "L2_LD.SELF.ANY.S_STATE",
0199 "SampleAfterValue": "200000",
0200 "UMask": "0x72"
0201 },
0202 {
0203 "BriefDescription": "L2 cache reads",
0204 "Counter": "0,1",
0205 "EventCode": "0x29",
0206 "EventName": "L2_LD.SELF.DEMAND.E_STATE",
0207 "SampleAfterValue": "200000",
0208 "UMask": "0x44"
0209 },
0210 {
0211 "BriefDescription": "L2 cache reads",
0212 "Counter": "0,1",
0213 "EventCode": "0x29",
0214 "EventName": "L2_LD.SELF.DEMAND.I_STATE",
0215 "SampleAfterValue": "200000",
0216 "UMask": "0x41"
0217 },
0218 {
0219 "BriefDescription": "L2 cache reads",
0220 "Counter": "0,1",
0221 "EventCode": "0x29",
0222 "EventName": "L2_LD.SELF.DEMAND.MESI",
0223 "SampleAfterValue": "200000",
0224 "UMask": "0x4f"
0225 },
0226 {
0227 "BriefDescription": "L2 cache reads",
0228 "Counter": "0,1",
0229 "EventCode": "0x29",
0230 "EventName": "L2_LD.SELF.DEMAND.M_STATE",
0231 "SampleAfterValue": "200000",
0232 "UMask": "0x48"
0233 },
0234 {
0235 "BriefDescription": "L2 cache reads",
0236 "Counter": "0,1",
0237 "EventCode": "0x29",
0238 "EventName": "L2_LD.SELF.DEMAND.S_STATE",
0239 "SampleAfterValue": "200000",
0240 "UMask": "0x42"
0241 },
0242 {
0243 "BriefDescription": "L2 cache reads",
0244 "Counter": "0,1",
0245 "EventCode": "0x29",
0246 "EventName": "L2_LD.SELF.PREFETCH.E_STATE",
0247 "SampleAfterValue": "200000",
0248 "UMask": "0x54"
0249 },
0250 {
0251 "BriefDescription": "L2 cache reads",
0252 "Counter": "0,1",
0253 "EventCode": "0x29",
0254 "EventName": "L2_LD.SELF.PREFETCH.I_STATE",
0255 "SampleAfterValue": "200000",
0256 "UMask": "0x51"
0257 },
0258 {
0259 "BriefDescription": "L2 cache reads",
0260 "Counter": "0,1",
0261 "EventCode": "0x29",
0262 "EventName": "L2_LD.SELF.PREFETCH.MESI",
0263 "SampleAfterValue": "200000",
0264 "UMask": "0x5f"
0265 },
0266 {
0267 "BriefDescription": "L2 cache reads",
0268 "Counter": "0,1",
0269 "EventCode": "0x29",
0270 "EventName": "L2_LD.SELF.PREFETCH.M_STATE",
0271 "SampleAfterValue": "200000",
0272 "UMask": "0x58"
0273 },
0274 {
0275 "BriefDescription": "L2 cache reads",
0276 "Counter": "0,1",
0277 "EventCode": "0x29",
0278 "EventName": "L2_LD.SELF.PREFETCH.S_STATE",
0279 "SampleAfterValue": "200000",
0280 "UMask": "0x52"
0281 },
0282 {
0283 "BriefDescription": "All read requests from L1 instruction and data caches",
0284 "Counter": "0,1",
0285 "EventCode": "0x2D",
0286 "EventName": "L2_LD_IFETCH.SELF.E_STATE",
0287 "SampleAfterValue": "200000",
0288 "UMask": "0x44"
0289 },
0290 {
0291 "BriefDescription": "All read requests from L1 instruction and data caches",
0292 "Counter": "0,1",
0293 "EventCode": "0x2D",
0294 "EventName": "L2_LD_IFETCH.SELF.I_STATE",
0295 "SampleAfterValue": "200000",
0296 "UMask": "0x41"
0297 },
0298 {
0299 "BriefDescription": "All read requests from L1 instruction and data caches",
0300 "Counter": "0,1",
0301 "EventCode": "0x2D",
0302 "EventName": "L2_LD_IFETCH.SELF.MESI",
0303 "SampleAfterValue": "200000",
0304 "UMask": "0x4f"
0305 },
0306 {
0307 "BriefDescription": "All read requests from L1 instruction and data caches",
0308 "Counter": "0,1",
0309 "EventCode": "0x2D",
0310 "EventName": "L2_LD_IFETCH.SELF.M_STATE",
0311 "SampleAfterValue": "200000",
0312 "UMask": "0x48"
0313 },
0314 {
0315 "BriefDescription": "All read requests from L1 instruction and data caches",
0316 "Counter": "0,1",
0317 "EventCode": "0x2D",
0318 "EventName": "L2_LD_IFETCH.SELF.S_STATE",
0319 "SampleAfterValue": "200000",
0320 "UMask": "0x42"
0321 },
0322 {
0323 "BriefDescription": "L2 cache misses.",
0324 "Counter": "0,1",
0325 "EventCode": "0x24",
0326 "EventName": "L2_LINES_IN.SELF.ANY",
0327 "SampleAfterValue": "200000",
0328 "UMask": "0x70"
0329 },
0330 {
0331 "BriefDescription": "L2 cache misses.",
0332 "Counter": "0,1",
0333 "EventCode": "0x24",
0334 "EventName": "L2_LINES_IN.SELF.DEMAND",
0335 "SampleAfterValue": "200000",
0336 "UMask": "0x40"
0337 },
0338 {
0339 "BriefDescription": "L2 cache misses.",
0340 "Counter": "0,1",
0341 "EventCode": "0x24",
0342 "EventName": "L2_LINES_IN.SELF.PREFETCH",
0343 "SampleAfterValue": "200000",
0344 "UMask": "0x50"
0345 },
0346 {
0347 "BriefDescription": "L2 cache lines evicted.",
0348 "Counter": "0,1",
0349 "EventCode": "0x26",
0350 "EventName": "L2_LINES_OUT.SELF.ANY",
0351 "SampleAfterValue": "200000",
0352 "UMask": "0x70"
0353 },
0354 {
0355 "BriefDescription": "L2 cache lines evicted.",
0356 "Counter": "0,1",
0357 "EventCode": "0x26",
0358 "EventName": "L2_LINES_OUT.SELF.DEMAND",
0359 "SampleAfterValue": "200000",
0360 "UMask": "0x40"
0361 },
0362 {
0363 "BriefDescription": "L2 cache lines evicted.",
0364 "Counter": "0,1",
0365 "EventCode": "0x26",
0366 "EventName": "L2_LINES_OUT.SELF.PREFETCH",
0367 "SampleAfterValue": "200000",
0368 "UMask": "0x50"
0369 },
0370 {
0371 "BriefDescription": "L2 locked accesses",
0372 "Counter": "0,1",
0373 "EventCode": "0x2B",
0374 "EventName": "L2_LOCK.SELF.E_STATE",
0375 "SampleAfterValue": "200000",
0376 "UMask": "0x44"
0377 },
0378 {
0379 "BriefDescription": "L2 locked accesses",
0380 "Counter": "0,1",
0381 "EventCode": "0x2B",
0382 "EventName": "L2_LOCK.SELF.I_STATE",
0383 "SampleAfterValue": "200000",
0384 "UMask": "0x41"
0385 },
0386 {
0387 "BriefDescription": "L2 locked accesses",
0388 "Counter": "0,1",
0389 "EventCode": "0x2B",
0390 "EventName": "L2_LOCK.SELF.MESI",
0391 "SampleAfterValue": "200000",
0392 "UMask": "0x4f"
0393 },
0394 {
0395 "BriefDescription": "L2 locked accesses",
0396 "Counter": "0,1",
0397 "EventCode": "0x2B",
0398 "EventName": "L2_LOCK.SELF.M_STATE",
0399 "SampleAfterValue": "200000",
0400 "UMask": "0x48"
0401 },
0402 {
0403 "BriefDescription": "L2 locked accesses",
0404 "Counter": "0,1",
0405 "EventCode": "0x2B",
0406 "EventName": "L2_LOCK.SELF.S_STATE",
0407 "SampleAfterValue": "200000",
0408 "UMask": "0x42"
0409 },
0410 {
0411 "BriefDescription": "L2 cache line modifications.",
0412 "Counter": "0,1",
0413 "EventCode": "0x25",
0414 "EventName": "L2_M_LINES_IN.SELF",
0415 "SampleAfterValue": "200000",
0416 "UMask": "0x40"
0417 },
0418 {
0419 "BriefDescription": "Modified lines evicted from the L2 cache",
0420 "Counter": "0,1",
0421 "EventCode": "0x27",
0422 "EventName": "L2_M_LINES_OUT.SELF.ANY",
0423 "SampleAfterValue": "200000",
0424 "UMask": "0x70"
0425 },
0426 {
0427 "BriefDescription": "Modified lines evicted from the L2 cache",
0428 "Counter": "0,1",
0429 "EventCode": "0x27",
0430 "EventName": "L2_M_LINES_OUT.SELF.DEMAND",
0431 "SampleAfterValue": "200000",
0432 "UMask": "0x40"
0433 },
0434 {
0435 "BriefDescription": "Modified lines evicted from the L2 cache",
0436 "Counter": "0,1",
0437 "EventCode": "0x27",
0438 "EventName": "L2_M_LINES_OUT.SELF.PREFETCH",
0439 "SampleAfterValue": "200000",
0440 "UMask": "0x50"
0441 },
0442 {
0443 "BriefDescription": "Cycles no L2 cache requests are pending",
0444 "Counter": "0,1",
0445 "EventCode": "0x32",
0446 "EventName": "L2_NO_REQ.SELF",
0447 "SampleAfterValue": "200000",
0448 "UMask": "0x40"
0449 },
0450 {
0451 "BriefDescription": "Rejected L2 cache requests",
0452 "Counter": "0,1",
0453 "EventCode": "0x30",
0454 "EventName": "L2_REJECT_BUSQ.SELF.ANY.E_STATE",
0455 "SampleAfterValue": "200000",
0456 "UMask": "0x74"
0457 },
0458 {
0459 "BriefDescription": "Rejected L2 cache requests",
0460 "Counter": "0,1",
0461 "EventCode": "0x30",
0462 "EventName": "L2_REJECT_BUSQ.SELF.ANY.I_STATE",
0463 "SampleAfterValue": "200000",
0464 "UMask": "0x71"
0465 },
0466 {
0467 "BriefDescription": "Rejected L2 cache requests",
0468 "Counter": "0,1",
0469 "EventCode": "0x30",
0470 "EventName": "L2_REJECT_BUSQ.SELF.ANY.MESI",
0471 "SampleAfterValue": "200000",
0472 "UMask": "0x7f"
0473 },
0474 {
0475 "BriefDescription": "Rejected L2 cache requests",
0476 "Counter": "0,1",
0477 "EventCode": "0x30",
0478 "EventName": "L2_REJECT_BUSQ.SELF.ANY.M_STATE",
0479 "SampleAfterValue": "200000",
0480 "UMask": "0x78"
0481 },
0482 {
0483 "BriefDescription": "Rejected L2 cache requests",
0484 "Counter": "0,1",
0485 "EventCode": "0x30",
0486 "EventName": "L2_REJECT_BUSQ.SELF.ANY.S_STATE",
0487 "SampleAfterValue": "200000",
0488 "UMask": "0x72"
0489 },
0490 {
0491 "BriefDescription": "Rejected L2 cache requests",
0492 "Counter": "0,1",
0493 "EventCode": "0x30",
0494 "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.E_STATE",
0495 "SampleAfterValue": "200000",
0496 "UMask": "0x44"
0497 },
0498 {
0499 "BriefDescription": "Rejected L2 cache requests",
0500 "Counter": "0,1",
0501 "EventCode": "0x30",
0502 "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.I_STATE",
0503 "SampleAfterValue": "200000",
0504 "UMask": "0x41"
0505 },
0506 {
0507 "BriefDescription": "Rejected L2 cache requests",
0508 "Counter": "0,1",
0509 "EventCode": "0x30",
0510 "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.MESI",
0511 "SampleAfterValue": "200000",
0512 "UMask": "0x4f"
0513 },
0514 {
0515 "BriefDescription": "Rejected L2 cache requests",
0516 "Counter": "0,1",
0517 "EventCode": "0x30",
0518 "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.M_STATE",
0519 "SampleAfterValue": "200000",
0520 "UMask": "0x48"
0521 },
0522 {
0523 "BriefDescription": "Rejected L2 cache requests",
0524 "Counter": "0,1",
0525 "EventCode": "0x30",
0526 "EventName": "L2_REJECT_BUSQ.SELF.DEMAND.S_STATE",
0527 "SampleAfterValue": "200000",
0528 "UMask": "0x42"
0529 },
0530 {
0531 "BriefDescription": "Rejected L2 cache requests",
0532 "Counter": "0,1",
0533 "EventCode": "0x30",
0534 "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.E_STATE",
0535 "SampleAfterValue": "200000",
0536 "UMask": "0x54"
0537 },
0538 {
0539 "BriefDescription": "Rejected L2 cache requests",
0540 "Counter": "0,1",
0541 "EventCode": "0x30",
0542 "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.I_STATE",
0543 "SampleAfterValue": "200000",
0544 "UMask": "0x51"
0545 },
0546 {
0547 "BriefDescription": "Rejected L2 cache requests",
0548 "Counter": "0,1",
0549 "EventCode": "0x30",
0550 "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.MESI",
0551 "SampleAfterValue": "200000",
0552 "UMask": "0x5f"
0553 },
0554 {
0555 "BriefDescription": "Rejected L2 cache requests",
0556 "Counter": "0,1",
0557 "EventCode": "0x30",
0558 "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.M_STATE",
0559 "SampleAfterValue": "200000",
0560 "UMask": "0x58"
0561 },
0562 {
0563 "BriefDescription": "Rejected L2 cache requests",
0564 "Counter": "0,1",
0565 "EventCode": "0x30",
0566 "EventName": "L2_REJECT_BUSQ.SELF.PREFETCH.S_STATE",
0567 "SampleAfterValue": "200000",
0568 "UMask": "0x52"
0569 },
0570 {
0571 "BriefDescription": "L2 cache requests",
0572 "Counter": "0,1",
0573 "EventCode": "0x2E",
0574 "EventName": "L2_RQSTS.SELF.ANY.E_STATE",
0575 "SampleAfterValue": "200000",
0576 "UMask": "0x74"
0577 },
0578 {
0579 "BriefDescription": "L2 cache requests",
0580 "Counter": "0,1",
0581 "EventCode": "0x2E",
0582 "EventName": "L2_RQSTS.SELF.ANY.I_STATE",
0583 "SampleAfterValue": "200000",
0584 "UMask": "0x71"
0585 },
0586 {
0587 "BriefDescription": "L2 cache requests",
0588 "Counter": "0,1",
0589 "EventCode": "0x2E",
0590 "EventName": "L2_RQSTS.SELF.ANY.MESI",
0591 "SampleAfterValue": "200000",
0592 "UMask": "0x7f"
0593 },
0594 {
0595 "BriefDescription": "L2 cache requests",
0596 "Counter": "0,1",
0597 "EventCode": "0x2E",
0598 "EventName": "L2_RQSTS.SELF.ANY.M_STATE",
0599 "SampleAfterValue": "200000",
0600 "UMask": "0x78"
0601 },
0602 {
0603 "BriefDescription": "L2 cache requests",
0604 "Counter": "0,1",
0605 "EventCode": "0x2E",
0606 "EventName": "L2_RQSTS.SELF.ANY.S_STATE",
0607 "SampleAfterValue": "200000",
0608 "UMask": "0x72"
0609 },
0610 {
0611 "BriefDescription": "L2 cache requests",
0612 "Counter": "0,1",
0613 "EventCode": "0x2E",
0614 "EventName": "L2_RQSTS.SELF.DEMAND.E_STATE",
0615 "SampleAfterValue": "200000",
0616 "UMask": "0x44"
0617 },
0618 {
0619 "BriefDescription": "L2 cache demand requests from this core that missed the L2",
0620 "Counter": "0,1",
0621 "EventCode": "0x2E",
0622 "EventName": "L2_RQSTS.SELF.DEMAND.I_STATE",
0623 "SampleAfterValue": "200000",
0624 "UMask": "0x41"
0625 },
0626 {
0627 "BriefDescription": "L2 cache demand requests from this core",
0628 "Counter": "0,1",
0629 "EventCode": "0x2E",
0630 "EventName": "L2_RQSTS.SELF.DEMAND.MESI",
0631 "SampleAfterValue": "200000",
0632 "UMask": "0x4f"
0633 },
0634 {
0635 "BriefDescription": "L2 cache requests",
0636 "Counter": "0,1",
0637 "EventCode": "0x2E",
0638 "EventName": "L2_RQSTS.SELF.DEMAND.M_STATE",
0639 "SampleAfterValue": "200000",
0640 "UMask": "0x48"
0641 },
0642 {
0643 "BriefDescription": "L2 cache requests",
0644 "Counter": "0,1",
0645 "EventCode": "0x2E",
0646 "EventName": "L2_RQSTS.SELF.DEMAND.S_STATE",
0647 "SampleAfterValue": "200000",
0648 "UMask": "0x42"
0649 },
0650 {
0651 "BriefDescription": "L2 cache requests",
0652 "Counter": "0,1",
0653 "EventCode": "0x2E",
0654 "EventName": "L2_RQSTS.SELF.PREFETCH.E_STATE",
0655 "SampleAfterValue": "200000",
0656 "UMask": "0x54"
0657 },
0658 {
0659 "BriefDescription": "L2 cache requests",
0660 "Counter": "0,1",
0661 "EventCode": "0x2E",
0662 "EventName": "L2_RQSTS.SELF.PREFETCH.I_STATE",
0663 "SampleAfterValue": "200000",
0664 "UMask": "0x51"
0665 },
0666 {
0667 "BriefDescription": "L2 cache requests",
0668 "Counter": "0,1",
0669 "EventCode": "0x2E",
0670 "EventName": "L2_RQSTS.SELF.PREFETCH.MESI",
0671 "SampleAfterValue": "200000",
0672 "UMask": "0x5f"
0673 },
0674 {
0675 "BriefDescription": "L2 cache requests",
0676 "Counter": "0,1",
0677 "EventCode": "0x2E",
0678 "EventName": "L2_RQSTS.SELF.PREFETCH.M_STATE",
0679 "SampleAfterValue": "200000",
0680 "UMask": "0x58"
0681 },
0682 {
0683 "BriefDescription": "L2 cache requests",
0684 "Counter": "0,1",
0685 "EventCode": "0x2E",
0686 "EventName": "L2_RQSTS.SELF.PREFETCH.S_STATE",
0687 "SampleAfterValue": "200000",
0688 "UMask": "0x52"
0689 },
0690 {
0691 "BriefDescription": "L2 store requests",
0692 "Counter": "0,1",
0693 "EventCode": "0x2A",
0694 "EventName": "L2_ST.SELF.E_STATE",
0695 "SampleAfterValue": "200000",
0696 "UMask": "0x44"
0697 },
0698 {
0699 "BriefDescription": "L2 store requests",
0700 "Counter": "0,1",
0701 "EventCode": "0x2A",
0702 "EventName": "L2_ST.SELF.I_STATE",
0703 "SampleAfterValue": "200000",
0704 "UMask": "0x41"
0705 },
0706 {
0707 "BriefDescription": "L2 store requests",
0708 "Counter": "0,1",
0709 "EventCode": "0x2A",
0710 "EventName": "L2_ST.SELF.MESI",
0711 "SampleAfterValue": "200000",
0712 "UMask": "0x4f"
0713 },
0714 {
0715 "BriefDescription": "L2 store requests",
0716 "Counter": "0,1",
0717 "EventCode": "0x2A",
0718 "EventName": "L2_ST.SELF.M_STATE",
0719 "SampleAfterValue": "200000",
0720 "UMask": "0x48"
0721 },
0722 {
0723 "BriefDescription": "L2 store requests",
0724 "Counter": "0,1",
0725 "EventCode": "0x2A",
0726 "EventName": "L2_ST.SELF.S_STATE",
0727 "SampleAfterValue": "200000",
0728 "UMask": "0x42"
0729 },
0730 {
0731 "BriefDescription": "Retired loads that hit the L2 cache (precise event).",
0732 "Counter": "0,1",
0733 "EventCode": "0xCB",
0734 "EventName": "MEM_LOAD_RETIRED.L2_HIT",
0735 "SampleAfterValue": "200000",
0736 "UMask": "0x1"
0737 },
0738 {
0739 "BriefDescription": "Retired loads that miss the L2 cache",
0740 "Counter": "0,1",
0741 "EventCode": "0xCB",
0742 "EventName": "MEM_LOAD_RETIRED.L2_MISS",
0743 "SampleAfterValue": "10000",
0744 "UMask": "0x2"
0745 }
0746 ]
