0001 [
0002 {
0003 "MetricName": "branch_misprediction_ratio",
0004 "BriefDescription": "Execution-Time Branch Misprediction Ratio (Non-Speculative)",
0005 "MetricExpr": "d_ratio(ex_ret_brn_misp, ex_ret_brn)",
0006 "MetricGroup": "branch_prediction",
0007 "ScaleUnit": "100%"
0008 },
0009 {
0010 "EventName": "all_data_cache_accesses",
0011 "EventCode": "0x29",
0012 "BriefDescription": "All L1 Data Cache Accesses",
0013 "UMask": "0x07"
0014 },
0015 {
0016 "MetricName": "all_l2_cache_accesses",
0017 "BriefDescription": "All L2 Cache Accesses",
0018 "MetricExpr": "l2_request_g1.all_no_prefetch + l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
0019 "MetricGroup": "l2_cache"
0020 },
0021 {
0022 "EventName": "l2_cache_accesses_from_ic_misses",
0023 "EventCode": "0x60",
0024 "BriefDescription": "L2 Cache Accesses from L1 Instruction Cache Misses (including prefetch)",
0025 "UMask": "0x10"
0026 },
0027 {
0028 "EventName": "l2_cache_accesses_from_dc_misses",
0029 "EventCode": "0x60",
0030 "BriefDescription": "L2 Cache Accesses from L1 Data Cache Misses (including prefetch)",
0031 "UMask": "0xe8"
0032 },
0033 {
0034 "MetricName": "l2_cache_accesses_from_l2_hwpf",
0035 "BriefDescription": "L2 Cache Accesses from L2 HWPF",
0036 "MetricExpr": "l2_pf_hit_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
0037 "MetricGroup": "l2_cache"
0038 },
0039 {
0040 "MetricName": "all_l2_cache_misses",
0041 "BriefDescription": "All L2 Cache Misses",
0042 "MetricExpr": "l2_cache_req_stat.ic_dc_miss_in_l2 + l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
0043 "MetricGroup": "l2_cache"
0044 },
0045 {
0046 "EventName": "l2_cache_misses_from_ic_miss",
0047 "EventCode": "0x64",
0048 "BriefDescription": "L2 Cache Misses from L1 Instruction Cache Misses",
0049 "UMask": "0x01"
0050 },
0051 {
0052 "EventName": "l2_cache_misses_from_dc_misses",
0053 "EventCode": "0x64",
0054 "BriefDescription": "L2 Cache Misses from L1 Data Cache Misses",
0055 "UMask": "0x08"
0056 },
0057 {
0058 "MetricName": "l2_cache_misses_from_l2_hwpf",
0059 "BriefDescription": "L2 Cache Misses from L2 Cache HWPF",
0060 "MetricExpr": "l2_pf_miss_l2_hit_l3 + l2_pf_miss_l2_l3",
0061 "MetricGroup": "l2_cache"
0062 },
0063 {
0064 "MetricName": "all_l2_cache_hits",
0065 "BriefDescription": "All L2 Cache Hits",
0066 "MetricExpr": "l2_cache_req_stat.ic_dc_hit_in_l2 + l2_pf_hit_l2",
0067 "MetricGroup": "l2_cache"
0068 },
0069 {
0070 "EventName": "l2_cache_hits_from_ic_misses",
0071 "EventCode": "0x64",
0072 "BriefDescription": "L2 Cache Hits from L1 Instruction Cache Misses",
0073 "UMask": "0x06"
0074 },
0075 {
0076 "EventName": "l2_cache_hits_from_dc_misses",
0077 "EventCode": "0x64",
0078 "BriefDescription": "L2 Cache Hits from L1 Data Cache Misses",
0079 "UMask": "0xf0"
0080 },
0081 {
0082 "EventName": "l2_cache_hits_from_l2_hwpf",
0083 "EventCode": "0x70",
0084 "BriefDescription": "L2 Cache Hits from L2 Cache HWPF",
0085 "UMask": "0xff"
0086 },
0087 {
0088 "EventName": "l3_cache_accesses",
0089 "EventCode": "0x04",
0090 "BriefDescription": "L3 Cache Accesses",
0091 "UMask": "0xff",
0092 "Unit": "L3PMC"
0093 },
0094 {
0095 "EventName": "l3_misses",
0096 "EventCode": "0x04",
0097 "BriefDescription": "L3 Misses (includes cacheline state change requests)",
0098 "UMask": "0x01",
0099 "Unit": "L3PMC"
0100 },
0101 {
0102 "MetricName": "l3_read_miss_latency",
0103 "BriefDescription": "Average L3 Read Miss Latency (in core clocks)",
0104 "MetricExpr": "(xi_sys_fill_latency * 16) / xi_ccx_sdp_req1",
0105 "MetricGroup": "l3_cache",
0106 "ScaleUnit": "1core clocks"
0107 },
0108 {
0109 "MetricName": "op_cache_fetch_miss_ratio",
0110 "BriefDescription": "Op Cache (64B) Fetch Miss Ratio",
0111 "MetricExpr": "d_ratio(op_cache_hit_miss.op_cache_miss, op_cache_hit_miss.all_op_cache_accesses)",
0112 "MetricGroup": "l2_cache"
0113 },
0114 {
0115 "MetricName": "ic_fetch_miss_ratio",
0116 "BriefDescription": "Instruction Cache (32B) Fetch Miss Ratio",
0117 "MetricExpr": "d_ratio(ic_tag_hit_miss.instruction_cache_miss, ic_tag_hit_miss.all_instruction_cache_accesses)",
0118 "MetricGroup": "l2_cache",
0119 "ScaleUnit": "100%"
0120 },
0121 {
0122 "EventName": "l1_data_cache_fills_from_memory",
0123 "EventCode": "0x44",
0124 "BriefDescription": "L1 Data Cache Fills: From Memory",
0125 "UMask": "0x48"
0126 },
0127 {
0128 "EventName": "l1_data_cache_fills_from_remote_node",
0129 "EventCode": "0x44",
0130 "BriefDescription": "L1 Data Cache Fills: From Remote Node",
0131 "UMask": "0x50"
0132 },
0133 {
0134 "EventName": "l1_data_cache_fills_from_within_same_ccx",
0135 "EventCode": "0x44",
0136 "BriefDescription": "L1 Data Cache Fills: From within same CCX",
0137 "UMask": "0x03"
0138 },
0139 {
0140 "EventName": "l1_data_cache_fills_from_external_ccx_cache",
0141 "EventCode": "0x44",
0142 "BriefDescription": "L1 Data Cache Fills: From External CCX Cache",
0143 "UMask": "0x14"
0144 },
0145 {
0146 "EventName": "l1_data_cache_fills_all",
0147 "EventCode": "0x44",
0148 "BriefDescription": "L1 Data Cache Fills: All",
0149 "UMask": "0xff"
0150 },
0151 {
0152 "MetricName": "l1_itlb_misses",
0153 "BriefDescription": "L1 ITLB Misses",
0154 "MetricExpr": "bp_l1_tlb_miss_l2_tlb_hit + bp_l1_tlb_miss_l2_tlb_miss",
0155 "MetricGroup": "tlb"
0156 },
0157 {
0158 "EventName": "l2_itlb_misses",
0159 "EventCode": "0x85",
0160 "BriefDescription": "L2 ITLB Misses & Instruction page walks",
0161 "UMask": "0x07"
0162 },
0163 {
0164 "EventName": "l1_dtlb_misses",
0165 "EventCode": "0x45",
0166 "BriefDescription": "L1 DTLB Misses",
0167 "UMask": "0xff"
0168 },
0169 {
0170 "EventName": "l2_dtlb_misses",
0171 "EventCode": "0x45",
0172 "BriefDescription": "L2 DTLB Misses & Data page walks",
0173 "UMask": "0xf0"
0174 },
0175 {
0176 "EventName": "all_tlbs_flushed",
0177 "EventCode": "0x78",
0178 "BriefDescription": "All TLBs Flushed",
0179 "UMask": "0xff"
0180 },
0181 {
0182 "MetricName": "macro_ops_dispatched",
0183 "BriefDescription": "Macro-ops Dispatched",
0184 "MetricExpr": "de_dis_cops_from_decoder.disp_op_type.any_integer_dispatch + de_dis_cops_from_decoder.disp_op_type.any_fp_dispatch",
0185 "MetricGroup": "decoder"
0186 },
0187 {
0188 "EventName": "sse_avx_stalls",
0189 "EventCode": "0x0e",
0190 "BriefDescription": "Mixed SSE/AVX Stalls",
0191 "UMask": "0x0e"
0192 },
0193 {
0194 "EventName": "macro_ops_retired",
0195 "EventCode": "0xc1",
0196 "BriefDescription": "Macro-ops Retired"
0197 },
0198 {
0199 "MetricName": "all_remote_links_outbound",
0200 "BriefDescription": "Approximate: Outbound data bytes for all Remote Links for a node (die)",
0201 "MetricExpr": "remote_outbound_data_controller_0 + remote_outbound_data_controller_1 + remote_outbound_data_controller_2 + remote_outbound_data_controller_3",
0202 "MetricGroup": "data_fabric",
0203 "PerPkg": "1",
0204 "ScaleUnit": "3e-5MiB"
0205 },
0206 {
0207 "MetricName": "nps1_die_to_dram",
0208 "BriefDescription": "Approximate: Combined DRAM B/bytes of all channels on a NPS1 node (die) (may need --metric-no-group)",
0209 "MetricExpr": "dram_channel_data_controller_0 + dram_channel_data_controller_1 + dram_channel_data_controller_2 + dram_channel_data_controller_3 + dram_channel_data_controller_4 + dram_channel_data_controller_5 + dram_channel_data_controller_6 + dram_channel_data_controller_7",
0210 "MetricGroup": "data_fabric",
0211 "PerPkg": "1",
0212 "ScaleUnit": "6.1e-5MiB"
0213 }
0214 ]
