0001 [
0002 {
0003 "EventName": "ls_bad_status2.stli_other",
0004 "EventCode": "0x24",
0005 "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.",
0006 "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.",
0007 "UMask": "0x02"
0008 },
0009 {
0010 "EventName": "ls_locks.spec_lock_hi_spec",
0011 "EventCode": "0x25",
0012 "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.",
0013 "UMask": "0x08"
0014 },
0015 {
0016 "EventName": "ls_locks.spec_lock_lo_spec",
0017 "EventCode": "0x25",
0018 "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.",
0019 "UMask": "0x04"
0020 },
0021 {
0022 "EventName": "ls_locks.non_spec_lock",
0023 "EventCode": "0x25",
0024 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
0025 "UMask": "0x02"
0026 },
0027 {
0028 "EventName": "ls_locks.bus_lock",
0029 "EventCode": "0x25",
0030 "BriefDescription": "Retired lock instructions. Comparable to legacy bus lock.",
0031 "UMask": "0x01"
0032 },
0033 {
0034 "EventName": "ls_ret_cl_flush",
0035 "EventCode": "0x26",
0036 "BriefDescription": "The number of retired CLFLUSH instructions. This is a non-speculative event."
0037 },
0038 {
0039 "EventName": "ls_ret_cpuid",
0040 "EventCode": "0x27",
0041 "BriefDescription": "The number of CPUID instructions retired."
0042 },
0043 {
0044 "EventName": "ls_dispatch.ld_st_dispatch",
0045 "EventCode": "0x29",
0046 "BriefDescription": "Load-op-Store Dispatch. Dispatch of a single op that performs a load from and store to the same memory address. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
0047 "UMask": "0x04"
0048 },
0049 {
0050 "EventName": "ls_dispatch.store_dispatch",
0051 "EventCode": "0x29",
0052 "BriefDescription": "Dispatch of a single op that performs a memory store. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
0053 "UMask": "0x02"
0054 },
0055 {
0056 "EventName": "ls_dispatch.ld_dispatch",
0057 "EventCode": "0x29",
0058 "BriefDescription": "Dispatch of a single op that performs a memory load. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
0059 "UMask": "0x01"
0060 },
0061 {
0062 "EventName": "ls_smi_rx",
0063 "EventCode": "0x2b",
0064 "BriefDescription": "Counts the number of SMIs received."
0065 },
0066 {
0067 "EventName": "ls_int_taken",
0068 "EventCode": "0x2c",
0069 "BriefDescription": "Counts the number of interrupts taken."
0070 },
0071 {
0072 "EventName": "ls_rdtsc",
0073 "EventCode": "0x2d",
0074 "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
0075 },
0076 {
0077 "EventName": "ls_stlf",
0078 "EventCode": "0x35",
0079 "BriefDescription": "Number of STLF hits."
0080 },
0081 {
0082 "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
0083 "EventCode": "0x37",
0084 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full.",
0085 "UMask": "0x01"
0086 },
0087 {
0088 "EventName": "ls_dc_accesses",
0089 "EventCode": "0x40",
0090 "BriefDescription": "Number of accesses to the dcache for load/store references.",
0091 "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
0092 },
0093 {
0094 "EventName": "ls_mab_alloc.all_allocations",
0095 "EventCode": "0x41",
0096 "BriefDescription": "All Allocations. Counts when a LS pipe allocates a MAB entry.",
0097 "UMask": "0x7f"
0098 },
0099 {
0100 "EventName": "ls_mab_alloc.hardware_prefetcher_allocations",
0101 "EventCode": "0x41",
0102 "BriefDescription": "Hardware Prefetcher Allocations. Counts when a LS pipe allocates a MAB entry.",
0103 "UMask": "0x40"
0104 },
0105 {
0106 "EventName": "ls_mab_alloc.load_store_allocations",
0107 "EventCode": "0x41",
0108 "BriefDescription": "Load Store Allocations. Counts when a LS pipe allocates a MAB entry.",
0109 "UMask": "0x3f"
0110 },
0111 {
0112 "EventName": "ls_mab_alloc.dc_prefetcher",
0113 "EventCode": "0x41",
0114 "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.",
0115 "UMask": "0x08"
0116 },
0117 {
0118 "EventName": "ls_mab_alloc.stores",
0119 "EventCode": "0x41",
0120 "BriefDescription": "LS MAB Allocates by Type. Stores.",
0121 "UMask": "0x02"
0122 },
0123 {
0124 "EventName": "ls_mab_alloc.loads",
0125 "EventCode": "0x41",
0126 "BriefDescription": "LS MAB Allocates by Type. Loads.",
0127 "UMask": "0x01"
0128 },
0129 {
0130 "EventName": "ls_dmnd_fills_from_sys.mem_io_remote",
0131 "EventCode": "0x43",
0132 "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
0133 "UMask": "0x40"
0134 },
0135 {
0136 "EventName": "ls_dmnd_fills_from_sys.ext_cache_remote",
0137 "EventCode": "0x43",
0138 "BriefDescription": "Demand Data Cache Fills by Data Source. From CCX Cache in different Node.",
0139 "UMask": "0x10"
0140 },
0141 {
0142 "EventName": "ls_dmnd_fills_from_sys.mem_io_local",
0143 "EventCode": "0x43",
0144 "BriefDescription": "Demand Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
0145 "UMask": "0x08"
0146 },
0147 {
0148 "EventName": "ls_dmnd_fills_from_sys.ext_cache_local",
0149 "EventCode": "0x43",
0150 "BriefDescription": "Demand Data Cache Fills by Data Source. From cache of different CCX in same node.",
0151 "UMask": "0x04"
0152 },
0153 {
0154 "EventName": "ls_dmnd_fills_from_sys.int_cache",
0155 "EventCode": "0x43",
0156 "BriefDescription": "Demand Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
0157 "UMask": "0x02"
0158 },
0159 {
0160 "EventName": "ls_dmnd_fills_from_sys.lcl_l2",
0161 "EventCode": "0x43",
0162 "BriefDescription": "Demand Data Cache Fills by Data Source. From Local L2 to the core.",
0163 "UMask": "0x01"
0164 },
0165 {
0166 "EventName": "ls_any_fills_from_sys.mem_io_remote",
0167 "EventCode": "0x44",
0168 "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
0169 "UMask": "0x40"
0170 },
0171 {
0172 "EventName": "ls_any_fills_from_sys.ext_cache_remote",
0173 "EventCode": "0x44",
0174 "BriefDescription": "Any Data Cache Fills by Data Source. From CCX Cache in different Node.",
0175 "UMask": "0x10"
0176 },
0177 {
0178 "EventName": "ls_any_fills_from_sys.mem_io_local",
0179 "EventCode": "0x44",
0180 "BriefDescription": "Any Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
0181 "UMask": "0x08"
0182 },
0183 {
0184 "EventName": "ls_any_fills_from_sys.ext_cache_local",
0185 "EventCode": "0x44",
0186 "BriefDescription": "Any Data Cache Fills by Data Source. From cache of different CCX in same node.",
0187 "UMask": "0x04"
0188 },
0189 {
0190 "EventName": "ls_any_fills_from_sys.int_cache",
0191 "EventCode": "0x44",
0192 "BriefDescription": "Any Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
0193 "UMask": "0x02"
0194 },
0195 {
0196 "EventName": "ls_any_fills_from_sys.lcl_l2",
0197 "EventCode": "0x44",
0198 "BriefDescription": "Any Data Cache Fills by Data Source. From Local L2 to the core.",
0199 "UMask": "0x01"
0200 },
0201 {
0202 "EventName": "ls_l1_d_tlb_miss.all",
0203 "EventCode": "0x45",
0204 "BriefDescription": "All L1 DTLB Misses or Reloads. Use l1_dtlb_misses instead.",
0205 "UMask": "0xff"
0206 },
0207 {
0208 "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
0209 "EventCode": "0x45",
0210 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that also missed in the L2 TLB.",
0211 "UMask": "0x80"
0212 },
0213 {
0214 "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
0215 "EventCode": "0x45",
0216 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that also missed in the L2 TLB.",
0217 "UMask": "0x40"
0218 },
0219 {
0220 "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
0221 "EventCode": "0x45",
0222 "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page that also missed in the L2 TLB.",
0223 "UMask": "0x20"
0224 },
0225 {
0226 "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
0227 "EventCode": "0x45",
0228 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that missed the L2 TLB.",
0229 "UMask": "0x10"
0230 },
0231 {
0232 "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
0233 "EventCode": "0x45",
0234 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.",
0235 "UMask": "0x08"
0236 },
0237 {
0238 "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
0239 "EventCode": "0x45",
0240 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.",
0241 "UMask": "0x04"
0242 },
0243 {
0244 "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
0245 "EventCode": "0x45",
0246 "BriefDescription": "L1 DTLB Miss. DTLB reload to a coalesced page that hit in the L2 TLB.",
0247 "UMask": "0x02"
0248 },
0249 {
0250 "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
0251 "EventCode": "0x45",
0252 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.",
0253 "UMask": "0x01"
0254 },
0255 {
0256 "EventName": "ls_tablewalker.iside",
0257 "EventCode": "0x46",
0258 "BriefDescription": "Total Page Table Walks on I-side.",
0259 "UMask": "0x0c"
0260 },
0261 {
0262 "EventName": "ls_tablewalker.ic_type1",
0263 "EventCode": "0x46",
0264 "BriefDescription": "Total Page Table Walks IC Type 1.",
0265 "UMask": "0x08"
0266 },
0267 {
0268 "EventName": "ls_tablewalker.ic_type0",
0269 "EventCode": "0x46",
0270 "BriefDescription": "Total Page Table Walks IC Type 0.",
0271 "UMask": "0x04"
0272 },
0273 {
0274 "EventName": "ls_tablewalker.dside",
0275 "EventCode": "0x46",
0276 "BriefDescription": "Total Page Table Walks on D-side.",
0277 "UMask": "0x03"
0278 },
0279 {
0280 "EventName": "ls_tablewalker.dc_type1",
0281 "EventCode": "0x46",
0282 "BriefDescription": "Total Page Table Walks DC Type 1.",
0283 "UMask": "0x02"
0284 },
0285 {
0286 "EventName": "ls_tablewalker.dc_type0",
0287 "EventCode": "0x46",
0288 "BriefDescription": "Total Page Table Walks DC Type 0.",
0289 "UMask": "0x01"
0290 },
0291 {
0292 "EventName": "ls_misal_loads.ma4k",
0293 "EventCode": "0x47",
0294 "BriefDescription": "The number of 4KB misaligned (i.e., page crossing) loads.",
0295 "UMask": "0x02"
0296 },
0297 {
0298 "EventName": "ls_misal_loads.ma64",
0299 "EventCode": "0x47",
0300 "BriefDescription": "The number of 64B misaligned (i.e., cacheline crossing) loads.",
0301 "UMask": "0x01"
0302 },
0303 {
0304 "EventName": "ls_pref_instr_disp",
0305 "EventCode": "0x4b",
0306 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).",
0307 "UMask": "0xff"
0308 },
0309 {
0310 "EventName": "ls_pref_instr_disp.prefetch_nta",
0311 "EventCode": "0x4b",
0312 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.",
0313 "UMask": "0x04"
0314 },
0315 {
0316 "EventName": "ls_pref_instr_disp.prefetch_w",
0317 "EventCode": "0x4b",
0318 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchW instruction. See docAPM3 PREFETCHW.",
0319 "UMask": "0x02"
0320 },
0321 {
0322 "EventName": "ls_pref_instr_disp.prefetch",
0323 "EventCode": "0x4b",
0324 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.",
0325 "UMask": "0x01"
0326 },
0327 {
0328 "EventName": "ls_inef_sw_pref.mab_mch_cnt",
0329 "EventCode": "0x52",
0330 "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",
0331 "UMask": "0x02"
0332 },
0333 {
0334 "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
0335 "EventCode": "0x52",
0336 "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",
0337 "UMask": "0x01"
0338 },
0339 {
0340 "EventName": "ls_sw_pf_dc_fills.mem_io_remote",
0341 "EventCode": "0x59",
0342 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
0343 "UMask": "0x40"
0344 },
0345 {
0346 "EventName": "ls_sw_pf_dc_fills.ext_cache_remote",
0347 "EventCode": "0x59",
0348 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.",
0349 "UMask": "0x10"
0350 },
0351 {
0352 "EventName": "ls_sw_pf_dc_fills.mem_io_local",
0353 "EventCode": "0x59",
0354 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
0355 "UMask": "0x08"
0356 },
0357 {
0358 "EventName": "ls_sw_pf_dc_fills.ext_cache_local",
0359 "EventCode": "0x59",
0360 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.",
0361 "UMask": "0x04"
0362 },
0363 {
0364 "EventName": "ls_sw_pf_dc_fills.int_cache",
0365 "EventCode": "0x59",
0366 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
0367 "UMask": "0x02"
0368 },
0369 {
0370 "EventName": "ls_sw_pf_dc_fills.lcl_l2",
0371 "EventCode": "0x59",
0372 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From Local L2 to the core.",
0373 "UMask": "0x01"
0374 },
0375 {
0376 "EventName": "ls_hw_pf_dc_fills.mem_io_remote",
0377 "EventCode": "0x5a",
0378 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in different Node.",
0379 "UMask": "0x40"
0380 },
0381 {
0382 "EventName": "ls_hw_pf_dc_fills.ext_cache_remote",
0383 "EventCode": "0x5a",
0384 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From CCX Cache in different Node.",
0385 "UMask": "0x10"
0386 },
0387 {
0388 "EventName": "ls_hw_pf_dc_fills.mem_io_local",
0389 "EventCode": "0x5a",
0390 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM or IO connected in same node.",
0391 "UMask": "0x08"
0392 },
0393 {
0394 "EventName": "ls_hw_pf_dc_fills.ext_cache_local",
0395 "EventCode": "0x5a",
0396 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From cache of different CCX in same node.",
0397 "UMask": "0x04"
0398 },
0399 {
0400 "EventName": "ls_hw_pf_dc_fills.int_cache",
0401 "EventCode": "0x5a",
0402 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From L3 or different L2 in same CCX.",
0403 "UMask": "0x02"
0404 },
0405 {
0406 "EventName": "ls_hw_pf_dc_fills.lcl_l2",
0407 "EventCode": "0x5a",
0408 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From Local L2 to the core.",
0409 "UMask": "0x01"
0410 },
0411 {
0412 "EventName": "ls_alloc_mab_count",
0413 "EventCode": "0x5f",
0414 "BriefDescription": "Count of Allocated Mabs",
0415 "PublicDescription": "This event counts the in-flight L1 data cache misses (allocated Miss Address Buffers) divided by 4 and rounded down each cycle unless used with the MergeEvent functionality. If the MergeEvent is used, it counts the exact number of outstanding L1 data cache misses. See 2.1.17.3 [Large Increment per Cycle Events]."
0416 },
0417 {
0418 "EventName": "ls_not_halted_cyc",
0419 "EventCode": "0x76",
0420 "BriefDescription": "Cycles not in Halt."
0421 },
0422 {
0423 "EventName": "ls_tlb_flush.all_tlb_flushes",
0424 "EventCode": "0x78",
0425 "BriefDescription": "All TLB Flushes. Requires unit mask 0xFF to engage event for counting. Use all_tlbs_flushed instead",
0426 "UMask": "0xff"
0427 }
0428 ]
