0001 [
0002 {
0003 "EventName": "ls_bad_status2.stli_other",
0004 "EventCode": "0x24",
0005 "BriefDescription": "Non-forwardable conflict; used to reduce STLI's via software. All reasons. Store To Load Interlock (STLI) are loads that were unable to complete because of a possible match with an older store, and the older store could not do STLF for some reason.",
0006 "PublicDescription" : "Store-to-load conflicts: A load was unable to complete due to a non-forwardable conflict with an older store. Most commonly, a load's address range partially but not completely overlaps with an uncompleted older store. Software can avoid this problem by using same-size and same-alignment loads and stores when accessing the same data. Vector/SIMD code is particularly susceptible to this problem; software should construct wide vector stores by manipulating vector elements in registers using shuffle/blend/swap instructions prior to storing to memory, instead of using narrow element-by-element stores.",
0007 "UMask": "0x02"
0008 },
0009 {
0010 "EventName": "ls_locks.spec_lock_hi_spec",
0011 "EventCode": "0x25",
0012 "BriefDescription": "Retired lock instructions. High speculative cacheable lock speculation succeeded.",
0013 "UMask": "0x08"
0014 },
0015 {
0016 "EventName": "ls_locks.spec_lock_lo_spec",
0017 "EventCode": "0x25",
0018 "BriefDescription": "Retired lock instructions. Low speculative cacheable lock speculation succeeded.",
0019 "UMask": "0x04"
0020 },
0021 {
0022 "EventName": "ls_locks.non_spec_lock",
0023 "EventCode": "0x25",
0024 "BriefDescription": "Retired lock instructions. Non-speculative lock succeeded.",
0025 "UMask": "0x02"
0026 },
0027 {
0028 "EventName": "ls_locks.bus_lock",
0029 "EventCode": "0x25",
0030 "BriefDescription": "Retired lock instructions. Bus lock when a locked operations crosses a cache boundary or is done on an uncacheable memory type. Comparable to legacy bus lock.",
0031 "UMask": "0x01"
0032 },
0033 {
0034 "EventName": "ls_ret_cl_flush",
0035 "EventCode": "0x26",
0036 "BriefDescription": "Number of retired CLFLUSH instructions."
0037 },
0038 {
0039 "EventName": "ls_ret_cpuid",
0040 "EventCode": "0x27",
0041 "BriefDescription": "Number of retired CPUID instructions."
0042 },
0043 {
0044 "EventName": "ls_dispatch.ld_st_dispatch",
0045 "EventCode": "0x29",
0046 "BriefDescription": "Dispatch of a single op that performs a load from and store to the same memory address. Number of single ops that do load/store to an address.",
0047 "UMask": "0x04"
0048 },
0049 {
0050 "EventName": "ls_dispatch.store_dispatch",
0051 "EventCode": "0x29",
0052 "BriefDescription": "Number of stores dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
0053 "UMask": "0x02"
0054 },
0055 {
0056 "EventName": "ls_dispatch.ld_dispatch",
0057 "EventCode": "0x29",
0058 "BriefDescription": "Number of loads dispatched. Counts the number of operations dispatched to the LS unit. Unit Masks ADDed.",
0059 "UMask": "0x01"
0060 },
0061 {
0062 "EventName": "ls_smi_rx",
0063 "EventCode": "0x2b",
0064 "BriefDescription": "Number of SMIs received."
0065 },
0066 {
0067 "EventName": "ls_int_taken",
0068 "EventCode": "0x2c",
0069 "BriefDescription": "Number of interrupts taken."
0070 },
0071 {
0072 "EventName": "ls_rdtsc",
0073 "EventCode": "0x2d",
0074 "BriefDescription": "Number of reads of the TSC (RDTSC instructions). The count is speculative."
0075 },
0076 {
0077 "EventName": "ls_stlf",
0078 "EventCode": "0x35",
0079 "BriefDescription": "Number of STLF hits."
0080 },
0081 {
0082 "EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
0083 "EventCode": "0x37",
0084 "BriefDescription": "A non-cacheable store and the non-cacheable commit buffer is full."
0085 },
0086 {
0087 "EventName": "ls_dc_accesses",
0088 "EventCode": "0x40",
0089 "BriefDescription": "Number of accesses to the dcache for load/store references.",
0090 "PublicDescription": "The number of accesses to the data cache for load and store references. This may include certain microcode scratchpad accesses, although these are generally rare. Each increment represents an eight-byte access, although the instruction may only be accessing a portion of that. This event is a speculative event."
0091 },
0092 {
0093 "EventName": "ls_mab_alloc.dc_prefetcher",
0094 "EventCode": "0x41",
0095 "BriefDescription": "LS MAB Allocates by Type. DC prefetcher.",
0096 "UMask": "0x08"
0097 },
0098 {
0099 "EventName": "ls_mab_alloc.stores",
0100 "EventCode": "0x41",
0101 "BriefDescription": "LS MAB Allocates by Type. Stores.",
0102 "UMask": "0x02"
0103 },
0104 {
0105 "EventName": "ls_mab_alloc.loads",
0106 "EventCode": "0x41",
0107 "BriefDescription": "LS MAB Allocates by Type. Loads.",
0108 "UMask": "0x01"
0109 },
0110 {
0111 "EventName": "ls_refills_from_sys.ls_mabresp_rmt_dram",
0112 "EventCode": "0x43",
0113 "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from different die.",
0114 "UMask": "0x40"
0115 },
0116 {
0117 "EventName": "ls_refills_from_sys.ls_mabresp_rmt_cache",
0118 "EventCode": "0x43",
0119 "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; Remote CCX and the address's Home Node is on a different die.",
0120 "UMask": "0x10"
0121 },
0122 {
0123 "EventName": "ls_refills_from_sys.ls_mabresp_lcl_dram",
0124 "EventCode": "0x43",
0125 "BriefDescription": "Demand Data Cache Fills by Data Source. DRAM or IO from this thread's die.",
0126 "UMask": "0x08"
0127 },
0128 {
0129 "EventName": "ls_refills_from_sys.ls_mabresp_lcl_cache",
0130 "EventCode": "0x43",
0131 "BriefDescription": "Demand Data Cache Fills by Data Source. Hit in cache; local CCX (not Local L2), or Remote CCX and the address's Home Node is on this thread's die.",
0132 "UMask": "0x02"
0133 },
0134 {
0135 "EventName": "ls_refills_from_sys.ls_mabresp_lcl_l2",
0136 "EventCode": "0x43",
0137 "BriefDescription": "Demand Data Cache Fills by Data Source. Local L2 hit.",
0138 "UMask": "0x01"
0139 },
0140 {
0141 "EventName": "ls_l1_d_tlb_miss.all",
0142 "EventCode": "0x45",
0143 "BriefDescription": "All L1 DTLB Misses or Reloads.",
0144 "UMask": "0xff"
0145 },
0146 {
0147 "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
0148 "EventCode": "0x45",
0149 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that miss in the L2 TLB.",
0150 "UMask": "0x80"
0151 },
0152 {
0153 "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
0154 "EventCode": "0x45",
0155 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that miss in the L2 TLB.",
0156 "UMask": "0x40"
0157 },
0158 {
0159 "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
0160 "EventCode": "0x45",
0161 "BriefDescription": "L1 DTLB Miss. DTLB reload coalesced page miss.",
0162 "UMask": "0x20"
0163 },
0164 {
0165 "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
0166 "EventCode": "0x45",
0167 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that miss the L2 TLB.",
0168 "UMask": "0x10"
0169 },
0170 {
0171 "EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
0172 "EventCode": "0x45",
0173 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 1G page that hit in the L2 TLB.",
0174 "UMask": "0x08"
0175 },
0176 {
0177 "EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
0178 "EventCode": "0x45",
0179 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 2M page that hit in the L2 TLB.",
0180 "UMask": "0x04"
0181 },
0182 {
0183 "EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
0184 "EventCode": "0x45",
0185 "BriefDescription": "L1 DTLB Miss. DTLB reload hit a coalesced page.",
0186 "UMask": "0x02"
0187 },
0188 {
0189 "EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
0190 "EventCode": "0x45",
0191 "BriefDescription": "L1 DTLB Miss. DTLB reload to a 4K page that hit in the L2 TLB.",
0192 "UMask": "0x01"
0193 },
0194 {
0195 "EventName": "ls_tablewalker.iside",
0196 "EventCode": "0x46",
0197 "BriefDescription": "Total Page Table Walks on I-side.",
0198 "UMask": "0x0c"
0199 },
0200 {
0201 "EventName": "ls_tablewalker.ic_type1",
0202 "EventCode": "0x46",
0203 "BriefDescription": "Total Page Table Walks IC Type 1.",
0204 "UMask": "0x08"
0205 },
0206 {
0207 "EventName": "ls_tablewalker.ic_type0",
0208 "EventCode": "0x46",
0209 "BriefDescription": "Total Page Table Walks IC Type 0.",
0210 "UMask": "0x04"
0211 },
0212 {
0213 "EventName": "ls_tablewalker.dside",
0214 "EventCode": "0x46",
0215 "BriefDescription": "Total Page Table Walks on D-side.",
0216 "UMask": "0x03"
0217 },
0218 {
0219 "EventName": "ls_tablewalker.dc_type1",
0220 "EventCode": "0x46",
0221 "BriefDescription": "Total Page Table Walks DC Type 1.",
0222 "UMask": "0x02"
0223 },
0224 {
0225 "EventName": "ls_tablewalker.dc_type0",
0226 "EventCode": "0x46",
0227 "BriefDescription": "Total Page Table Walks DC Type 0.",
0228 "UMask": "0x01"
0229 },
0230 {
0231 "EventName": "ls_misal_accesses",
0232 "EventCode": "0x47",
0233 "BriefDescription": "Misaligned loads."
0234 },
0235 {
0236 "EventName": "ls_pref_instr_disp",
0237 "EventCode": "0x4b",
0238 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative).",
0239 "UMask": "0xff"
0240 },
0241 {
0242 "EventName": "ls_pref_instr_disp.prefetch_nta",
0243 "EventCode": "0x4b",
0244 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). PrefetchNTA instruction. See docAPM3 PREFETCHlevel.",
0245 "UMask": "0x04"
0246 },
0247 {
0248 "EventName": "ls_pref_instr_disp.prefetch_w",
0249 "EventCode": "0x4b",
0250 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). See docAPM3 PREFETCHW.",
0251 "UMask": "0x02"
0252 },
0253 {
0254 "EventName": "ls_pref_instr_disp.prefetch",
0255 "EventCode": "0x4b",
0256 "BriefDescription": "Software Prefetch Instructions Dispatched (Speculative). Prefetch_T0_T1_T2. PrefetchT0, T1 and T2 instructions. See docAPM3 PREFETCHlevel.",
0257 "UMask": "0x01"
0258 },
0259 {
0260 "EventName": "ls_inef_sw_pref.mab_mch_cnt",
0261 "EventCode": "0x52",
0262 "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a match on an already-allocated miss request buffer.",
0263 "UMask": "0x02"
0264 },
0265 {
0266 "EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
0267 "EventCode": "0x52",
0268 "BriefDescription": "The number of software prefetches that did not fetch data outside of the processor core. Software PREFETCH instruction saw a DC hit.",
0269 "UMask": "0x01"
0270 },
0271 {
0272 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_dram",
0273 "EventCode": "0x59",
0274 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
0275 "UMask": "0x40"
0276 },
0277 {
0278 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_rmt_cache",
0279 "EventCode": "0x59",
0280 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
0281 "UMask": "0x10"
0282 },
0283 {
0284 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_dram",
0285 "EventCode": "0x59",
0286 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. DRAM or IO from this thread's die. From DRAM (home node local).",
0287 "UMask": "0x08"
0288 },
0289 {
0290 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_cache",
0291 "EventCode": "0x59",
0292 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
0293 "UMask": "0x02"
0294 },
0295 {
0296 "EventName": "ls_sw_pf_dc_fill.ls_mabresp_lcl_l2",
0297 "EventCode": "0x59",
0298 "BriefDescription": "Software Prefetch Data Cache Fills by Data Source. Local L2 hit.",
0299 "UMask": "0x01"
0300 },
0301 {
0302 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_dram",
0303 "EventCode": "0x5a",
0304 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node remote).",
0305 "UMask": "0x40"
0306 },
0307 {
0308 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_rmt_cache",
0309 "EventCode": "0x5a",
0310 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node remote).",
0311 "UMask": "0x10"
0312 },
0313 {
0314 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_dram",
0315 "EventCode": "0x5a",
0316 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From DRAM (home node local).",
0317 "UMask": "0x08"
0318 },
0319 {
0320 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_cache",
0321 "EventCode": "0x5a",
0322 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. From another cache (home node local).",
0323 "UMask": "0x02"
0324 },
0325 {
0326 "EventName": "ls_hw_pf_dc_fill.ls_mabresp_lcl_l2",
0327 "EventCode": "0x5a",
0328 "BriefDescription": "Hardware Prefetch Data Cache Fills by Data Source. Local L2 hit.",
0329 "UMask": "0x01"
0330 },
0331 {
0332 "EventName": "ls_not_halted_cyc",
0333 "EventCode": "0x76",
0334 "BriefDescription": "Cycles not in Halt."
0335 },
0336 {
0337 "EventName": "ls_tlb_flush",
0338 "EventCode": "0x78",
0339 "BriefDescription": "All TLB Flushes"
0340 }
0341 ]
