0001 [
0002 {
0003 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5",
0006 "EventCode": "0x08",
0007 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
0008 "PEBScounters": "0,1,2,3,4,5",
0009 "SampleAfterValue": "200003",
0010 "Speculative": "1",
0011 "UMask": "0xe",
0012 "Unit": "cpu_atom"
0013 },
0014 {
0015 "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
0016 "CollectPEBSRecord": "2",
0017 "Counter": "0,1,2,3,4,5",
0018 "EventCode": "0x49",
0019 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
0020 "PEBScounters": "0,1,2,3,4,5",
0021 "SampleAfterValue": "2000003",
0022 "Speculative": "1",
0023 "UMask": "0xe",
0024 "Unit": "cpu_atom"
0025 },
0026 {
0027 "BriefDescription": "Counts the number of page walks initiated by a instruction fetch that missed the first and second level TLBs.",
0028 "CollectPEBSRecord": "2",
0029 "Counter": "0,1,2,3,4,5",
0030 "EventCode": "0x85",
0031 "EventName": "ITLB_MISSES.MISS_CAUSED_WALK",
0032 "PEBScounters": "0,1,2,3,4,5",
0033 "SampleAfterValue": "1000003",
0034 "Speculative": "1",
0035 "UMask": "0x1",
0036 "Unit": "cpu_atom"
0037 },
0038 {
0039 "BriefDescription": "Counts the number of page walks due to an instruction fetch that miss the PDE (Page Directory Entry) cache.",
0040 "CollectPEBSRecord": "2",
0041 "Counter": "0,1,2,3,4,5",
0042 "EventCode": "0x85",
0043 "EventName": "ITLB_MISSES.PDE_CACHE_MISS",
0044 "PEBScounters": "0,1,2,3,4,5",
0045 "SampleAfterValue": "2000003",
0046 "Speculative": "1",
0047 "UMask": "0x80",
0048 "Unit": "cpu_atom"
0049 },
0050 {
0051 "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
0052 "CollectPEBSRecord": "2",
0053 "Counter": "0,1,2,3,4,5",
0054 "EventCode": "0x85",
0055 "EventName": "ITLB_MISSES.WALK_COMPLETED",
0056 "PEBScounters": "0,1,2,3,4,5",
0057 "SampleAfterValue": "200003",
0058 "Speculative": "1",
0059 "UMask": "0xe",
0060 "Unit": "cpu_atom"
0061 },
0062 {
0063 "BriefDescription": "Counts the number of cycles that the head (oldest load) of the load buffer and retirement are both stalled due to a DTLB miss.",
0064 "CollectPEBSRecord": "2",
0065 "Counter": "0,1,2,3,4,5",
0066 "EventCode": "0x05",
0067 "EventName": "LD_HEAD.DTLB_MISS_AT_RET",
0068 "PEBScounters": "0,1,2,3,4,5",
0069 "SampleAfterValue": "1000003",
0070 "Speculative": "1",
0071 "UMask": "0x90",
0072 "Unit": "cpu_atom"
0073 },
0074 {
0075 "BriefDescription": "Loads that miss the DTLB and hit the STLB.",
0076 "CollectPEBSRecord": "2",
0077 "Counter": "0,1,2,3",
0078 "EventCode": "0x12",
0079 "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
0080 "PEBScounters": "0,1,2,3",
0081 "SampleAfterValue": "100003",
0082 "Speculative": "1",
0083 "UMask": "0x20",
0084 "Unit": "cpu_core"
0085 },
0086 {
0087 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a demand load.",
0088 "CollectPEBSRecord": "2",
0089 "Counter": "0,1,2,3",
0090 "CounterMask": "1",
0091 "EventCode": "0x12",
0092 "EventName": "DTLB_LOAD_MISSES.WALK_ACTIVE",
0093 "PEBScounters": "0,1,2,3",
0094 "SampleAfterValue": "100003",
0095 "Speculative": "1",
0096 "UMask": "0x10",
0097 "Unit": "cpu_core"
0098 },
0099 {
0100 "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
0101 "CollectPEBSRecord": "2",
0102 "Counter": "0,1,2,3",
0103 "EventCode": "0x12",
0104 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
0105 "PEBScounters": "0,1,2,3",
0106 "SampleAfterValue": "100003",
0107 "Speculative": "1",
0108 "UMask": "0xe",
0109 "Unit": "cpu_core"
0110 },
0111 {
0112 "BriefDescription": "Page walks completed due to a demand data load to a 1G page.",
0113 "CollectPEBSRecord": "2",
0114 "Counter": "0,1,2,3",
0115 "EventCode": "0x12",
0116 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
0117 "PEBScounters": "0,1,2,3",
0118 "SampleAfterValue": "100003",
0119 "Speculative": "1",
0120 "UMask": "0x8",
0121 "Unit": "cpu_core"
0122 },
0123 {
0124 "BriefDescription": "Page walks completed due to a demand data load to a 2M/4M page.",
0125 "CollectPEBSRecord": "2",
0126 "Counter": "0,1,2,3",
0127 "EventCode": "0x12",
0128 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
0129 "PEBScounters": "0,1,2,3",
0130 "SampleAfterValue": "100003",
0131 "Speculative": "1",
0132 "UMask": "0x4",
0133 "Unit": "cpu_core"
0134 },
0135 {
0136 "BriefDescription": "Page walks completed due to a demand data load to a 4K page.",
0137 "CollectPEBSRecord": "2",
0138 "Counter": "0,1,2,3",
0139 "EventCode": "0x12",
0140 "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
0141 "PEBScounters": "0,1,2,3",
0142 "SampleAfterValue": "100003",
0143 "Speculative": "1",
0144 "UMask": "0x2",
0145 "Unit": "cpu_core"
0146 },
0147 {
0148 "BriefDescription": "Number of page walks outstanding for a demand load in the PMH each cycle.",
0149 "CollectPEBSRecord": "2",
0150 "Counter": "0,1,2,3",
0151 "EventCode": "0x12",
0152 "EventName": "DTLB_LOAD_MISSES.WALK_PENDING",
0153 "PEBScounters": "0,1,2,3",
0154 "SampleAfterValue": "100003",
0155 "Speculative": "1",
0156 "UMask": "0x10",
0157 "Unit": "cpu_core"
0158 },
0159 {
0160 "BriefDescription": "Stores that miss the DTLB and hit the STLB.",
0161 "CollectPEBSRecord": "2",
0162 "Counter": "0,1,2,3",
0163 "EventCode": "0x13",
0164 "EventName": "DTLB_STORE_MISSES.STLB_HIT",
0165 "PEBScounters": "0,1,2,3",
0166 "SampleAfterValue": "100003",
0167 "Speculative": "1",
0168 "UMask": "0x20",
0169 "Unit": "cpu_core"
0170 },
0171 {
0172 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for a store.",
0173 "CollectPEBSRecord": "2",
0174 "Counter": "0,1,2,3",
0175 "CounterMask": "1",
0176 "EventCode": "0x13",
0177 "EventName": "DTLB_STORE_MISSES.WALK_ACTIVE",
0178 "PEBScounters": "0,1,2,3",
0179 "SampleAfterValue": "100003",
0180 "Speculative": "1",
0181 "UMask": "0x10",
0182 "Unit": "cpu_core"
0183 },
0184 {
0185 "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
0186 "CollectPEBSRecord": "2",
0187 "Counter": "0,1,2,3",
0188 "EventCode": "0x13",
0189 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
0190 "PEBScounters": "0,1,2,3",
0191 "SampleAfterValue": "100003",
0192 "Speculative": "1",
0193 "UMask": "0xe",
0194 "Unit": "cpu_core"
0195 },
0196 {
0197 "BriefDescription": "Page walks completed due to a demand data store to a 1G page.",
0198 "CollectPEBSRecord": "2",
0199 "Counter": "0,1,2,3",
0200 "EventCode": "0x13",
0201 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
0202 "PEBScounters": "0,1,2,3",
0203 "SampleAfterValue": "100003",
0204 "Speculative": "1",
0205 "UMask": "0x8",
0206 "Unit": "cpu_core"
0207 },
0208 {
0209 "BriefDescription": "Page walks completed due to a demand data store to a 2M/4M page.",
0210 "CollectPEBSRecord": "2",
0211 "Counter": "0,1,2,3",
0212 "EventCode": "0x13",
0213 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
0214 "PEBScounters": "0,1,2,3",
0215 "SampleAfterValue": "100003",
0216 "Speculative": "1",
0217 "UMask": "0x4",
0218 "Unit": "cpu_core"
0219 },
0220 {
0221 "BriefDescription": "Page walks completed due to a demand data store to a 4K page.",
0222 "CollectPEBSRecord": "2",
0223 "Counter": "0,1,2,3",
0224 "EventCode": "0x13",
0225 "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
0226 "PEBScounters": "0,1,2,3",
0227 "SampleAfterValue": "100003",
0228 "Speculative": "1",
0229 "UMask": "0x2",
0230 "Unit": "cpu_core"
0231 },
0232 {
0233 "BriefDescription": "Number of page walks outstanding for a store in the PMH each cycle.",
0234 "CollectPEBSRecord": "2",
0235 "Counter": "0,1,2,3",
0236 "EventCode": "0x13",
0237 "EventName": "DTLB_STORE_MISSES.WALK_PENDING",
0238 "PEBScounters": "0,1,2,3",
0239 "SampleAfterValue": "100003",
0240 "Speculative": "1",
0241 "UMask": "0x10",
0242 "Unit": "cpu_core"
0243 },
0244 {
0245 "BriefDescription": "Instruction fetch requests that miss the ITLB and hit the STLB.",
0246 "CollectPEBSRecord": "2",
0247 "Counter": "0,1,2,3",
0248 "EventCode": "0x11",
0249 "EventName": "ITLB_MISSES.STLB_HIT",
0250 "PEBScounters": "0,1,2,3",
0251 "SampleAfterValue": "100003",
0252 "Speculative": "1",
0253 "UMask": "0x20",
0254 "Unit": "cpu_core"
0255 },
0256 {
0257 "BriefDescription": "Cycles when at least one PMH is busy with a page walk for code (instruction fetch) request.",
0258 "CollectPEBSRecord": "2",
0259 "Counter": "0,1,2,3",
0260 "CounterMask": "1",
0261 "EventCode": "0x11",
0262 "EventName": "ITLB_MISSES.WALK_ACTIVE",
0263 "PEBScounters": "0,1,2,3",
0264 "SampleAfterValue": "100003",
0265 "Speculative": "1",
0266 "UMask": "0x10",
0267 "Unit": "cpu_core"
0268 },
0269 {
0270 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
0271 "CollectPEBSRecord": "2",
0272 "Counter": "0,1,2,3",
0273 "EventCode": "0x11",
0274 "EventName": "ITLB_MISSES.WALK_COMPLETED",
0275 "PEBScounters": "0,1,2,3",
0276 "SampleAfterValue": "100003",
0277 "Speculative": "1",
0278 "UMask": "0xe",
0279 "Unit": "cpu_core"
0280 },
0281 {
0282 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
0283 "CollectPEBSRecord": "2",
0284 "Counter": "0,1,2,3",
0285 "EventCode": "0x11",
0286 "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
0287 "PEBScounters": "0,1,2,3",
0288 "SampleAfterValue": "100003",
0289 "Speculative": "1",
0290 "UMask": "0x4",
0291 "Unit": "cpu_core"
0292 },
0293 {
0294 "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
0295 "CollectPEBSRecord": "2",
0296 "Counter": "0,1,2,3",
0297 "EventCode": "0x11",
0298 "EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
0299 "PEBScounters": "0,1,2,3",
0300 "SampleAfterValue": "100003",
0301 "Speculative": "1",
0302 "UMask": "0x2",
0303 "Unit": "cpu_core"
0304 },
0305 {
0306 "BriefDescription": "Number of page walks outstanding for an outstanding code request in the PMH each cycle.",
0307 "CollectPEBSRecord": "2",
0308 "Counter": "0,1,2,3",
0309 "EventCode": "0x11",
0310 "EventName": "ITLB_MISSES.WALK_PENDING",
0311 "PEBScounters": "0,1,2,3",
0312 "SampleAfterValue": "100003",
0313 "Speculative": "1",
0314 "UMask": "0x10",
0315 "Unit": "cpu_core"
0316 }
0317 ]
