0001 [
0002 {
0003 "BriefDescription": "Number of clocks",
0004 "Counter": "0,1,2,3,4",
0005 "CounterType": "PGMABLE",
0006 "EventCode": "0x01",
0007 "EventName": "UNC_M_CLOCKTICKS",
0008 "PerPkg": "1",
0009 "Unit": "iMC"
0010 },
0011 {
0012 "BriefDescription": "Incoming VC0 read request",
0013 "Counter": "0,1,2,3,4",
0014 "CounterType": "PGMABLE",
0015 "EventCode": "0x02",
0016 "EventName": "UNC_M_VC0_REQUESTS_RD",
0017 "PerPkg": "1",
0018 "Unit": "iMC"
0019 },
0020 {
0021 "BriefDescription": "Incoming VC0 write request",
0022 "Counter": "0,1,2,3,4",
0023 "CounterType": "PGMABLE",
0024 "EventCode": "0x03",
0025 "EventName": "UNC_M_VC0_REQUESTS_WR",
0026 "PerPkg": "1",
0027 "Unit": "iMC"
0028 },
0029 {
0030 "BriefDescription": "Incoming VC1 read request",
0031 "Counter": "0,1,2,3,4",
0032 "CounterType": "PGMABLE",
0033 "EventCode": "0x04",
0034 "EventName": "UNC_M_VC1_REQUESTS_RD",
0035 "PerPkg": "1",
0036 "Unit": "iMC"
0037 },
0038 {
0039 "BriefDescription": "Incoming VC1 write request",
0040 "Counter": "0,1,2,3,4",
0041 "CounterType": "PGMABLE",
0042 "EventCode": "0x05",
0043 "EventName": "UNC_M_VC1_REQUESTS_WR",
0044 "PerPkg": "1",
0045 "Unit": "iMC"
0046 },
0047 {
0048 "BriefDescription": "Incoming read prefetch request from IA",
0049 "Counter": "0,1,2,3,4",
0050 "CounterType": "PGMABLE",
0051 "EventCode": "0x0A",
0052 "EventName": "UNC_M_PREFETCH_RD",
0053 "PerPkg": "1",
0054 "Unit": "iMC"
0055 },
0056 {
0057 "BriefDescription": "Any Rank at Hot state",
0058 "Counter": "0,1,2,3,4",
0059 "CounterType": "PGMABLE",
0060 "EventCode": "0x19",
0061 "EventName": "UNC_M_DRAM_THERMAL_HOT",
0062 "PerPkg": "1",
0063 "Unit": "iMC"
0064 },
0065 {
0066 "BriefDescription": "Any Rank at Warm state",
0067 "Counter": "0,1,2,3,4",
0068 "CounterType": "PGMABLE",
0069 "EventCode": "0x1A",
0070 "EventName": "UNC_M_DRAM_THERMAL_WARM",
0071 "PerPkg": "1",
0072 "Unit": "iMC"
0073 },
0074 {
0075 "BriefDescription": "incoming read request page status is Page Hit",
0076 "Counter": "0,1,2,3,4",
0077 "CounterType": "PGMABLE",
0078 "EventCode": "0x1C",
0079 "EventName": "UNC_M_DRAM_PAGE_HIT_RD",
0080 "PerPkg": "1",
0081 "Unit": "iMC"
0082 },
0083 {
0084 "BriefDescription": "incoming read request page status is Page Empty",
0085 "Counter": "0,1,2,3,4",
0086 "CounterType": "PGMABLE",
0087 "EventCode": "0x1D",
0088 "EventName": "UNC_M_DRAM_PAGE_EMPTY_RD",
0089 "PerPkg": "1",
0090 "Unit": "iMC"
0091 },
0092 {
0093 "BriefDescription": "incoming read request page status is Page Miss",
0094 "Counter": "0,1,2,3,4",
0095 "CounterType": "PGMABLE",
0096 "EventCode": "0x1E",
0097 "EventName": "UNC_M_DRAM_PAGE_MISS_RD",
0098 "PerPkg": "1",
0099 "Unit": "iMC"
0100 },
0101 {
0102 "BriefDescription": "incoming write request page status is Page Hit",
0103 "Counter": "0,1,2,3,4",
0104 "CounterType": "PGMABLE",
0105 "EventCode": "0x1F",
0106 "EventName": "UNC_M_DRAM_PAGE_HIT_WR",
0107 "PerPkg": "1",
0108 "Unit": "iMC"
0109 },
0110 {
0111 "BriefDescription": "incoming write request page status is Page Empty",
0112 "Counter": "0,1,2,3,4",
0113 "CounterType": "PGMABLE",
0114 "EventCode": "0x20",
0115 "EventName": "UNC_M_DRAM_PAGE_EMPTY_WR",
0116 "PerPkg": "1",
0117 "Unit": "iMC"
0118 },
0119 {
0120 "BriefDescription": "incoming write request page status is Page Miss",
0121 "Counter": "0,1,2,3,4",
0122 "CounterType": "PGMABLE",
0123 "EventCode": "0x21",
0124 "EventName": "UNC_M_DRAM_PAGE_MISS_WR",
0125 "PerPkg": "1",
0126 "Unit": "iMC"
0127 },
0128 {
0129 "BriefDescription": "Read CAS command sent to DRAM",
0130 "Counter": "0,1,2,3,4",
0131 "CounterType": "PGMABLE",
0132 "EventCode": "0x22",
0133 "EventName": "UNC_M_CAS_COUNT_RD",
0134 "PerPkg": "1",
0135 "Unit": "iMC"
0136 },
0137 {
0138 "BriefDescription": "Write CAS command sent to DRAM",
0139 "Counter": "0,1,2,3,4",
0140 "CounterType": "PGMABLE",
0141 "EventCode": "0x23",
0142 "EventName": "UNC_M_CAS_COUNT_WR",
0143 "PerPkg": "1",
0144 "Unit": "iMC"
0145 },
0146 {
0147 "BriefDescription": "ACT command for a read request sent to DRAM",
0148 "Counter": "0,1,2,3,4",
0149 "CounterType": "PGMABLE",
0150 "EventCode": "0x24",
0151 "EventName": "UNC_M_ACT_COUNT_RD",
0152 "PerPkg": "1",
0153 "Unit": "iMC"
0154 },
0155 {
0156 "BriefDescription": "ACT command for a write request sent to DRAM",
0157 "Counter": "0,1,2,3,4",
0158 "CounterType": "PGMABLE",
0159 "EventCode": "0x25",
0160 "EventName": "UNC_M_ACT_COUNT_WR",
0161 "PerPkg": "1",
0162 "Unit": "iMC"
0163 },
0164 {
0165 "BriefDescription": "ACT command sent to DRAM",
0166 "Counter": "0,1,2,3,4",
0167 "CounterType": "PGMABLE",
0168 "EventCode": "0x26",
0169 "EventName": "UNC_M_ACT_COUNT_TOTAL",
0170 "PerPkg": "1",
0171 "Unit": "iMC"
0172 },
0173 {
0174 "BriefDescription": "PRE command sent to DRAM for a read/write request",
0175 "Counter": "0,1,2,3,4",
0176 "CounterType": "PGMABLE",
0177 "EventCode": "0x27",
0178 "EventName": "UNC_M_PRE_COUNT_PAGE_MISS",
0179 "PerPkg": "1",
0180 "Unit": "iMC"
0181 },
0182 {
0183 "BriefDescription": "PRE command sent to DRAM due to page table idle timer expiration",
0184 "Counter": "0,1,2,3,4",
0185 "CounterType": "PGMABLE",
0186 "EventCode": "0x28",
0187 "EventName": "UNC_M_PRE_COUNT_IDLE",
0188 "PerPkg": "1",
0189 "Unit": "iMC"
0190 },
0191 {
0192 "BriefDescription": "Counts every 64B read request entering the Memory Controller 0 to DRAM (sum of all channels)",
0193 "CounterType": "FREERUN",
0194 "EventName": "UNC_MC0_RDCAS_COUNT_FREERUN",
0195 "PerPkg": "1",
0196 "Unit": "iMC"
0197 },
0198 {
0199 "BriefDescription": "Counts every 64B read request entering the Memory Controller 1 to DRAM (sum of all channels)",
0200 "Counter": "3",
0201 "CounterType": "FREERUN",
0202 "EventName": "UNC_MC1_RDCAS_COUNT_FREERUN",
0203 "PerPkg": "1",
0204 "Unit": "iMC"
0205 },
0206 {
0207 "BriefDescription": "Counts every 64B write request entering the Memory Controller 0 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM",
0208 "Counter": "1",
0209 "CounterType": "FREERUN",
0210 "EventName": "UNC_MC0_WRCAS_COUNT_FREERUN",
0211 "PerPkg": "1",
0212 "Unit": "iMC"
0213 },
0214 {
0215 "BriefDescription": "Counts every 64B write request entering the Memory Controller 1 to DRAM (sum of all channels). Each write request counts as a new request incrementing this counter. However, same cache line write requests (both full and partial) are combined to a single 64 byte data transfer to DRAM",
0216 "Counter": "4",
0217 "CounterType": "FREERUN",
0218 "EventName": "UNC_MC1_WRCAS_COUNT_FREERUN",
0219 "PerPkg": "1",
0220 "Unit": "iMC"
0221 }
0222 ]
