0001 [
0002 {
0003 "BriefDescription": "Counts the total number of BACLEARS due to all branch types including conditional and unconditional jumps, returns, and indirect branches.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5",
0006 "EventCode": "0xe6",
0007 "EventName": "BACLEARS.ANY",
0008 "PEBScounters": "0,1,2,3,4,5",
0009 "SampleAfterValue": "100003",
0010 "Speculative": "1",
0011 "UMask": "0x1",
0012 "Unit": "cpu_atom"
0013 },
0014 {
0015 "BriefDescription": "Counts the number of requests to the instruction cache for one or more bytes of a cache line.",
0016 "CollectPEBSRecord": "2",
0017 "Counter": "0,1,2,3,4,5",
0018 "EventCode": "0x80",
0019 "EventName": "ICACHE.ACCESSES",
0020 "PEBScounters": "0,1,2,3,4,5",
0021 "SampleAfterValue": "200003",
0022 "Speculative": "1",
0023 "UMask": "0x3",
0024 "Unit": "cpu_atom"
0025 },
0026 {
0027 "BriefDescription": "Counts the number of instruction cache misses.",
0028 "CollectPEBSRecord": "2",
0029 "Counter": "0,1,2,3,4,5",
0030 "EventCode": "0x80",
0031 "EventName": "ICACHE.MISSES",
0032 "PEBScounters": "0,1,2,3,4,5",
0033 "SampleAfterValue": "200003",
0034 "Speculative": "1",
0035 "UMask": "0x2",
0036 "Unit": "cpu_atom"
0037 },
0038 {
0039 "BriefDescription": "Stalls caused by changing prefix length of the instruction.",
0040 "CollectPEBSRecord": "2",
0041 "Counter": "0,1,2,3",
0042 "EventCode": "0x87",
0043 "EventName": "DECODE.LCP",
0044 "PEBScounters": "0,1,2,3",
0045 "SampleAfterValue": "500009",
0046 "Speculative": "1",
0047 "UMask": "0x1",
0048 "Unit": "cpu_core"
0049 },
0050 {
0051 "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
0052 "CollectPEBSRecord": "2",
0053 "Counter": "0,1,2,3",
0054 "EventCode": "0x61",
0055 "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
0056 "PEBScounters": "0,1,2,3",
0057 "SampleAfterValue": "100003",
0058 "Speculative": "1",
0059 "UMask": "0x2",
0060 "Unit": "cpu_core"
0061 },
0062 {
0063 "BriefDescription": "Retired Instructions who experienced DSB miss.",
0064 "CollectPEBSRecord": "2",
0065 "Counter": "0,1,2,3,4,5,6,7",
0066 "EventCode": "0xc6",
0067 "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
0068 "MSRIndex": "0x3F7",
0069 "MSRValue": "0x1",
0070 "PEBS": "1",
0071 "PEBScounters": "0,1,2,3,4,5,6,7",
0072 "SampleAfterValue": "100007",
0073 "TakenAlone": "1",
0074 "UMask": "0x1",
0075 "Unit": "cpu_core"
0076 },
0077 {
0078 "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
0079 "CollectPEBSRecord": "2",
0080 "Counter": "0,1,2,3,4,5,6,7",
0081 "EventCode": "0xc6",
0082 "EventName": "FRONTEND_RETIRED.DSB_MISS",
0083 "MSRIndex": "0x3F7",
0084 "MSRValue": "0x11",
0085 "PEBS": "1",
0086 "PEBScounters": "0,1,2,3,4,5,6,7",
0087 "SampleAfterValue": "100007",
0088 "TakenAlone": "1",
0089 "UMask": "0x1",
0090 "Unit": "cpu_core"
0091 },
0092 {
0093 "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
0094 "CollectPEBSRecord": "2",
0095 "Counter": "0,1,2,3,4,5,6,7",
0096 "EventCode": "0xc6",
0097 "EventName": "FRONTEND_RETIRED.ITLB_MISS",
0098 "MSRIndex": "0x3F7",
0099 "MSRValue": "0x14",
0100 "PEBS": "1",
0101 "PEBScounters": "0,1,2,3,4,5,6,7",
0102 "SampleAfterValue": "100007",
0103 "TakenAlone": "1",
0104 "UMask": "0x1",
0105 "Unit": "cpu_core"
0106 },
0107 {
0108 "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
0109 "CollectPEBSRecord": "2",
0110 "Counter": "0,1,2,3,4,5,6,7",
0111 "EventCode": "0xc6",
0112 "EventName": "FRONTEND_RETIRED.L1I_MISS",
0113 "MSRIndex": "0x3F7",
0114 "MSRValue": "0x12",
0115 "PEBS": "1",
0116 "PEBScounters": "0,1,2,3,4,5,6,7",
0117 "SampleAfterValue": "100007",
0118 "TakenAlone": "1",
0119 "UMask": "0x1",
0120 "Unit": "cpu_core"
0121 },
0122 {
0123 "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
0124 "CollectPEBSRecord": "2",
0125 "Counter": "0,1,2,3,4,5,6,7",
0126 "EventCode": "0xc6",
0127 "EventName": "FRONTEND_RETIRED.L2_MISS",
0128 "MSRIndex": "0x3F7",
0129 "MSRValue": "0x13",
0130 "PEBS": "1",
0131 "PEBScounters": "0,1,2,3,4,5,6,7",
0132 "SampleAfterValue": "100007",
0133 "TakenAlone": "1",
0134 "UMask": "0x1",
0135 "Unit": "cpu_core"
0136 },
0137 {
0138 "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
0139 "CollectPEBSRecord": "2",
0140 "Counter": "0,1,2,3,4,5,6,7",
0141 "EventCode": "0xc6",
0142 "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
0143 "MSRIndex": "0x3F7",
0144 "MSRValue": "0x600106",
0145 "PEBS": "1",
0146 "PEBScounters": "0,1,2,3,4,5,6,7",
0147 "SampleAfterValue": "100007",
0148 "TakenAlone": "1",
0149 "UMask": "0x1",
0150 "Unit": "cpu_core"
0151 },
0152 {
0153 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
0154 "CollectPEBSRecord": "2",
0155 "Counter": "0,1,2,3,4,5,6,7",
0156 "EventCode": "0xc6",
0157 "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
0158 "MSRIndex": "0x3F7",
0159 "MSRValue": "0x608006",
0160 "PEBS": "1",
0161 "PEBScounters": "0,1,2,3,4,5,6,7",
0162 "SampleAfterValue": "100007",
0163 "TakenAlone": "1",
0164 "UMask": "0x1",
0165 "Unit": "cpu_core"
0166 },
0167 {
0168 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
0169 "CollectPEBSRecord": "2",
0170 "Counter": "0,1,2,3,4,5,6,7",
0171 "EventCode": "0xc6",
0172 "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
0173 "MSRIndex": "0x3F7",
0174 "MSRValue": "0x601006",
0175 "PEBS": "1",
0176 "PEBScounters": "0,1,2,3,4,5,6,7",
0177 "SampleAfterValue": "100007",
0178 "TakenAlone": "1",
0179 "UMask": "0x1",
0180 "Unit": "cpu_core"
0181 },
0182 {
0183 "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
0184 "CollectPEBSRecord": "2",
0185 "Counter": "0,1,2,3,4,5,6,7",
0186 "EventCode": "0xc6",
0187 "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
0188 "MSRIndex": "0x3F7",
0189 "MSRValue": "0x600206",
0190 "PEBS": "1",
0191 "PEBScounters": "0,1,2,3,4,5,6,7",
0192 "SampleAfterValue": "100007",
0193 "TakenAlone": "1",
0194 "UMask": "0x1",
0195 "Unit": "cpu_core"
0196 },
0197 {
0198 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
0199 "CollectPEBSRecord": "2",
0200 "Counter": "0,1,2,3,4,5,6,7",
0201 "EventCode": "0xc6",
0202 "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
0203 "MSRIndex": "0x3F7",
0204 "MSRValue": "0x610006",
0205 "PEBS": "1",
0206 "PEBScounters": "0,1,2,3,4,5,6,7",
0207 "SampleAfterValue": "100007",
0208 "TakenAlone": "1",
0209 "UMask": "0x1",
0210 "Unit": "cpu_core"
0211 },
0212 {
0213 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
0214 "CollectPEBSRecord": "2",
0215 "Counter": "0,1,2,3,4,5,6,7",
0216 "EventCode": "0xc6",
0217 "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
0218 "MSRIndex": "0x3F7",
0219 "MSRValue": "0x100206",
0220 "PEBS": "1",
0221 "PEBScounters": "0,1,2,3,4,5,6,7",
0222 "SampleAfterValue": "100007",
0223 "TakenAlone": "1",
0224 "UMask": "0x1",
0225 "Unit": "cpu_core"
0226 },
0227 {
0228 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
0229 "CollectPEBSRecord": "2",
0230 "Counter": "0,1,2,3,4,5,6,7",
0231 "EventCode": "0xc6",
0232 "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
0233 "MSRIndex": "0x3F7",
0234 "MSRValue": "0x602006",
0235 "PEBS": "1",
0236 "PEBScounters": "0,1,2,3,4,5,6,7",
0237 "SampleAfterValue": "100007",
0238 "TakenAlone": "1",
0239 "UMask": "0x1",
0240 "Unit": "cpu_core"
0241 },
0242 {
0243 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
0244 "CollectPEBSRecord": "2",
0245 "Counter": "0,1,2,3,4,5,6,7",
0246 "EventCode": "0xc6",
0247 "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
0248 "MSRIndex": "0x3F7",
0249 "MSRValue": "0x600406",
0250 "PEBS": "1",
0251 "PEBScounters": "0,1,2,3,4,5,6,7",
0252 "SampleAfterValue": "100007",
0253 "TakenAlone": "1",
0254 "UMask": "0x1",
0255 "Unit": "cpu_core"
0256 },
0257 {
0258 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
0259 "CollectPEBSRecord": "2",
0260 "Counter": "0,1,2,3,4,5,6,7",
0261 "EventCode": "0xc6",
0262 "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
0263 "MSRIndex": "0x3F7",
0264 "MSRValue": "0x620006",
0265 "PEBS": "1",
0266 "PEBScounters": "0,1,2,3,4,5,6,7",
0267 "SampleAfterValue": "100007",
0268 "TakenAlone": "1",
0269 "UMask": "0x1",
0270 "Unit": "cpu_core"
0271 },
0272 {
0273 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
0274 "CollectPEBSRecord": "2",
0275 "Counter": "0,1,2,3,4,5,6,7",
0276 "EventCode": "0xc6",
0277 "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
0278 "MSRIndex": "0x3F7",
0279 "MSRValue": "0x604006",
0280 "PEBS": "1",
0281 "PEBScounters": "0,1,2,3,4,5,6,7",
0282 "SampleAfterValue": "100007",
0283 "TakenAlone": "1",
0284 "UMask": "0x1",
0285 "Unit": "cpu_core"
0286 },
0287 {
0288 "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
0289 "CollectPEBSRecord": "2",
0290 "Counter": "0,1,2,3,4,5,6,7",
0291 "EventCode": "0xc6",
0292 "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
0293 "MSRIndex": "0x3F7",
0294 "MSRValue": "0x600806",
0295 "PEBS": "1",
0296 "PEBScounters": "0,1,2,3,4,5,6,7",
0297 "SampleAfterValue": "100007",
0298 "TakenAlone": "1",
0299 "UMask": "0x1",
0300 "Unit": "cpu_core"
0301 },
0302 {
0303 "BriefDescription": "FRONTEND_RETIRED.MS_FLOWS",
0304 "CollectPEBSRecord": "2",
0305 "Counter": "0,1,2,3,4,5,6,7",
0306 "EventCode": "0xc6",
0307 "EventName": "FRONTEND_RETIRED.MS_FLOWS",
0308 "MSRIndex": "0x3F7",
0309 "MSRValue": "0x8",
0310 "PEBS": "1",
0311 "PEBScounters": "0,1,2,3,4,5,6,7",
0312 "SampleAfterValue": "100007",
0313 "TakenAlone": "1",
0314 "UMask": "0x1",
0315 "Unit": "cpu_core"
0316 },
0317 {
0318 "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
0319 "CollectPEBSRecord": "2",
0320 "Counter": "0,1,2,3,4,5,6,7",
0321 "EventCode": "0xc6",
0322 "EventName": "FRONTEND_RETIRED.STLB_MISS",
0323 "MSRIndex": "0x3F7",
0324 "MSRValue": "0x15",
0325 "PEBS": "1",
0326 "PEBScounters": "0,1,2,3,4,5,6,7",
0327 "SampleAfterValue": "100007",
0328 "TakenAlone": "1",
0329 "UMask": "0x1",
0330 "Unit": "cpu_core"
0331 },
0332 {
0333 "BriefDescription": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
0334 "CollectPEBSRecord": "2",
0335 "Counter": "0,1,2,3,4,5,6,7",
0336 "EventCode": "0xc6",
0337 "EventName": "FRONTEND_RETIRED.UNKNOWN_BRANCH",
0338 "MSRIndex": "0x3F7",
0339 "MSRValue": "0x17",
0340 "PEBS": "1",
0341 "PEBScounters": "0,1,2,3,4,5,6,7",
0342 "SampleAfterValue": "100007",
0343 "TakenAlone": "1",
0344 "UMask": "0x1",
0345 "Unit": "cpu_core"
0346 },
0347 {
0348 "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss.",
0349 "CollectPEBSRecord": "2",
0350 "Counter": "0,1,2,3",
0351 "EventCode": "0x80",
0352 "EventName": "ICACHE_DATA.STALLS",
0353 "PEBScounters": "0,1,2,3",
0354 "SampleAfterValue": "500009",
0355 "Speculative": "1",
0356 "UMask": "0x4",
0357 "Unit": "cpu_core"
0358 },
0359 {
0360 "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss.",
0361 "CollectPEBSRecord": "2",
0362 "Counter": "0,1,2,3",
0363 "EventCode": "0x83",
0364 "EventName": "ICACHE_TAG.STALLS",
0365 "PEBScounters": "0,1,2,3",
0366 "SampleAfterValue": "200003",
0367 "Speculative": "1",
0368 "UMask": "0x4",
0369 "Unit": "cpu_core"
0370 },
0371 {
0372 "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
0373 "CollectPEBSRecord": "2",
0374 "Counter": "0,1,2,3",
0375 "CounterMask": "1",
0376 "EventCode": "0x79",
0377 "EventName": "IDQ.DSB_CYCLES_ANY",
0378 "PEBScounters": "0,1,2,3",
0379 "SampleAfterValue": "2000003",
0380 "Speculative": "1",
0381 "UMask": "0x8",
0382 "Unit": "cpu_core"
0383 },
0384 {
0385 "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
0386 "CollectPEBSRecord": "2",
0387 "Counter": "0,1,2,3",
0388 "CounterMask": "6",
0389 "EventCode": "0x79",
0390 "EventName": "IDQ.DSB_CYCLES_OK",
0391 "PEBScounters": "0,1,2,3",
0392 "SampleAfterValue": "2000003",
0393 "Speculative": "1",
0394 "UMask": "0x8",
0395 "Unit": "cpu_core"
0396 },
0397 {
0398 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
0399 "CollectPEBSRecord": "2",
0400 "Counter": "0,1,2,3",
0401 "EventCode": "0x79",
0402 "EventName": "IDQ.DSB_UOPS",
0403 "PEBScounters": "0,1,2,3",
0404 "SampleAfterValue": "2000003",
0405 "Speculative": "1",
0406 "UMask": "0x8",
0407 "Unit": "cpu_core"
0408 },
0409 {
0410 "BriefDescription": "Cycles MITE is delivering any Uop",
0411 "CollectPEBSRecord": "2",
0412 "Counter": "0,1,2,3",
0413 "CounterMask": "1",
0414 "EventCode": "0x79",
0415 "EventName": "IDQ.MITE_CYCLES_ANY",
0416 "PEBScounters": "0,1,2,3",
0417 "SampleAfterValue": "2000003",
0418 "Speculative": "1",
0419 "UMask": "0x4",
0420 "Unit": "cpu_core"
0421 },
0422 {
0423 "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
0424 "CollectPEBSRecord": "2",
0425 "Counter": "0,1,2,3",
0426 "CounterMask": "6",
0427 "EventCode": "0x79",
0428 "EventName": "IDQ.MITE_CYCLES_OK",
0429 "PEBScounters": "0,1,2,3",
0430 "SampleAfterValue": "2000003",
0431 "Speculative": "1",
0432 "UMask": "0x4",
0433 "Unit": "cpu_core"
0434 },
0435 {
0436 "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
0437 "CollectPEBSRecord": "2",
0438 "Counter": "0,1,2,3",
0439 "EventCode": "0x79",
0440 "EventName": "IDQ.MITE_UOPS",
0441 "PEBScounters": "0,1,2,3",
0442 "SampleAfterValue": "2000003",
0443 "Speculative": "1",
0444 "UMask": "0x4",
0445 "Unit": "cpu_core"
0446 },
0447 {
0448 "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
0449 "CollectPEBSRecord": "2",
0450 "Counter": "0,1,2,3",
0451 "CounterMask": "1",
0452 "EventCode": "0x79",
0453 "EventName": "IDQ.MS_CYCLES_ANY",
0454 "PEBScounters": "0,1,2,3",
0455 "SampleAfterValue": "2000003",
0456 "Speculative": "1",
0457 "UMask": "0x20",
0458 "Unit": "cpu_core"
0459 },
0460 {
0461 "BriefDescription": "Number of switches from DSB or MITE to the MS",
0462 "CollectPEBSRecord": "2",
0463 "Counter": "0,1,2,3",
0464 "CounterMask": "1",
0465 "EdgeDetect": "1",
0466 "EventCode": "0x79",
0467 "EventName": "IDQ.MS_SWITCHES",
0468 "PEBScounters": "0,1,2,3",
0469 "SampleAfterValue": "100003",
0470 "Speculative": "1",
0471 "UMask": "0x20",
0472 "Unit": "cpu_core"
0473 },
0474 {
0475 "BriefDescription": "Uops delivered to IDQ while MS is busy",
0476 "CollectPEBSRecord": "2",
0477 "Counter": "0,1,2,3",
0478 "EventCode": "0x79",
0479 "EventName": "IDQ.MS_UOPS",
0480 "PEBScounters": "0,1,2,3",
0481 "SampleAfterValue": "1000003",
0482 "Speculative": "1",
0483 "UMask": "0x20",
0484 "Unit": "cpu_core"
0485 },
0486 {
0487 "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
0488 "CollectPEBSRecord": "2",
0489 "Counter": "0,1,2,3,4,5,6,7",
0490 "EventCode": "0x9c",
0491 "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
0492 "PEBScounters": "0,1,2,3,4,5,6,7",
0493 "SampleAfterValue": "1000003",
0494 "Speculative": "1",
0495 "UMask": "0x1",
0496 "Unit": "cpu_core"
0497 },
0498 {
0499 "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
0500 "CollectPEBSRecord": "2",
0501 "Counter": "0,1,2,3,4,5,6,7",
0502 "CounterMask": "6",
0503 "EventCode": "0x9c",
0504 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
0505 "PEBScounters": "0,1,2,3,4,5,6,7",
0506 "SampleAfterValue": "1000003",
0507 "Speculative": "1",
0508 "UMask": "0x1",
0509 "Unit": "cpu_core"
0510 },
0511 {
0512 "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
0513 "CollectPEBSRecord": "2",
0514 "Counter": "0,1,2,3,4,5,6,7",
0515 "CounterMask": "1",
0516 "EventCode": "0x9c",
0517 "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
0518 "Invert": "1",
0519 "PEBScounters": "0,1,2,3,4,5,6,7",
0520 "SampleAfterValue": "1000003",
0521 "Speculative": "1",
0522 "UMask": "0x1",
0523 "Unit": "cpu_core"
0524 }
0525 ]
