0001 [
0002 {
0003 "BriefDescription": "Counts the number of floating point operations retired that required microcode assist.",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5",
0006 "EventCode": "0xc3",
0007 "EventName": "MACHINE_CLEARS.FP_ASSIST",
0008 "PEBScounters": "0,1,2,3,4,5",
0009 "SampleAfterValue": "20003",
0010 "Speculative": "1",
0011 "UMask": "0x4",
0012 "Unit": "cpu_atom"
0013 },
0014 {
0015 "BriefDescription": "Counts the number of floating point divide uops retired (x87 and SSE, including x87 sqrt).",
0016 "CollectPEBSRecord": "2",
0017 "Counter": "0,1,2,3,4,5",
0018 "EventCode": "0xc2",
0019 "EventName": "UOPS_RETIRED.FPDIV",
0020 "PEBS": "1",
0021 "PEBScounters": "0,1,2,3,4,5",
0022 "SampleAfterValue": "2000003",
0023 "UMask": "0x8",
0024 "Unit": "cpu_atom"
0025 },
0026 {
0027 "BriefDescription": "ARITH.FPDIV_ACTIVE",
0028 "CollectPEBSRecord": "2",
0029 "Counter": "0,1,2,3,4,5,6,7",
0030 "CounterMask": "1",
0031 "EventCode": "0xb0",
0032 "EventName": "ARITH.FPDIV_ACTIVE",
0033 "PEBScounters": "0,1,2,3,4,5,6,7",
0034 "SampleAfterValue": "1000003",
0035 "Speculative": "1",
0036 "UMask": "0x1",
0037 "Unit": "cpu_core"
0038 },
0039 {
0040 "BriefDescription": "Counts all microcode FP assists.",
0041 "CollectPEBSRecord": "2",
0042 "Counter": "0,1,2,3,4,5,6,7",
0043 "EventCode": "0xc1",
0044 "EventName": "ASSISTS.FP",
0045 "PEBScounters": "0,1,2,3,4,5,6,7",
0046 "SampleAfterValue": "100003",
0047 "Speculative": "1",
0048 "UMask": "0x2",
0049 "Unit": "cpu_core"
0050 },
0051 {
0052 "BriefDescription": "ASSISTS.SSE_AVX_MIX",
0053 "CollectPEBSRecord": "2",
0054 "Counter": "0,1,2,3,4,5,6,7",
0055 "EventCode": "0xc1",
0056 "EventName": "ASSISTS.SSE_AVX_MIX",
0057 "PEBScounters": "0,1,2,3,4,5,6,7",
0058 "SampleAfterValue": "1000003",
0059 "Speculative": "1",
0060 "UMask": "0x10",
0061 "Unit": "cpu_core"
0062 },
0063 {
0064 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_0",
0065 "CollectPEBSRecord": "2",
0066 "Counter": "0,1,2,3,4,5,6,7",
0067 "EventCode": "0xb3",
0068 "EventName": "FP_ARITH_DISPATCHED.PORT_0",
0069 "PEBScounters": "0,1,2,3,4,5,6,7",
0070 "SampleAfterValue": "2000003",
0071 "Speculative": "1",
0072 "UMask": "0x1",
0073 "Unit": "cpu_core"
0074 },
0075 {
0076 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_1",
0077 "CollectPEBSRecord": "2",
0078 "Counter": "0,1,2,3,4,5,6,7",
0079 "EventCode": "0xb3",
0080 "EventName": "FP_ARITH_DISPATCHED.PORT_1",
0081 "PEBScounters": "0,1,2,3,4,5,6,7",
0082 "SampleAfterValue": "2000003",
0083 "Speculative": "1",
0084 "UMask": "0x2",
0085 "Unit": "cpu_core"
0086 },
0087 {
0088 "BriefDescription": "FP_ARITH_DISPATCHED.PORT_5",
0089 "CollectPEBSRecord": "2",
0090 "Counter": "0,1,2,3,4,5,6,7",
0091 "EventCode": "0xb3",
0092 "EventName": "FP_ARITH_DISPATCHED.PORT_5",
0093 "PEBScounters": "0,1,2,3,4,5,6,7",
0094 "SampleAfterValue": "2000003",
0095 "Speculative": "1",
0096 "UMask": "0x4",
0097 "Unit": "cpu_core"
0098 },
0099 {
0100 "BriefDescription": "Counts number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 2 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0101 "CollectPEBSRecord": "2",
0102 "Counter": "0,1,2,3,4,5,6,7",
0103 "EventCode": "0xc7",
0104 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
0105 "PEBScounters": "0,1,2,3,4,5,6,7",
0106 "SampleAfterValue": "100003",
0107 "UMask": "0x4",
0108 "Unit": "cpu_core"
0109 },
0110 {
0111 "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP14 RSQRT14 SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0112 "CollectPEBSRecord": "2",
0113 "Counter": "0,1,2,3,4,5,6,7",
0114 "EventCode": "0xc7",
0115 "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
0116 "PEBScounters": "0,1,2,3,4,5,6,7",
0117 "SampleAfterValue": "100003",
0118 "UMask": "0x8",
0119 "Unit": "cpu_core"
0120 },
0121 {
0122 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 4 computation operations, one for each element. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0123 "CollectPEBSRecord": "2",
0124 "Counter": "0,1,2,3,4,5,6,7",
0125 "EventCode": "0xc7",
0126 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
0127 "PEBScounters": "0,1,2,3,4,5,6,7",
0128 "SampleAfterValue": "100003",
0129 "UMask": "0x10",
0130 "Unit": "cpu_core"
0131 },
0132 {
0133 "BriefDescription": "Counts number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 8 computation operations, one for each element. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB HADD HSUB SUBADD MUL DIV MIN MAX SQRT RSQRT RCP DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0134 "CollectPEBSRecord": "2",
0135 "Counter": "0,1,2,3,4,5,6,7",
0136 "EventCode": "0xc7",
0137 "EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
0138 "PEBScounters": "0,1,2,3,4,5,6,7",
0139 "SampleAfterValue": "100003",
0140 "UMask": "0x20",
0141 "Unit": "cpu_core"
0142 },
0143 {
0144 "BriefDescription": "Counts number of SSE/AVX computational scalar double precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0145 "CollectPEBSRecord": "2",
0146 "Counter": "0,1,2,3,4,5,6,7",
0147 "EventCode": "0xc7",
0148 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
0149 "PEBScounters": "0,1,2,3,4,5,6,7",
0150 "SampleAfterValue": "100003",
0151 "UMask": "0x1",
0152 "Unit": "cpu_core"
0153 },
0154 {
0155 "BriefDescription": "Counts number of SSE/AVX computational scalar single precision floating-point instructions retired; some instructions will count twice as noted below. Each count represents 1 computational operation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT RSQRT RCP FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform 2 calculations per element.",
0156 "CollectPEBSRecord": "2",
0157 "Counter": "0,1,2,3,4,5,6,7",
0158 "EventCode": "0xc7",
0159 "EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
0160 "PEBScounters": "0,1,2,3,4,5,6,7",
0161 "SampleAfterValue": "100003",
0162 "UMask": "0x2",
0163 "Unit": "cpu_core"
0164 }
0165 ]
