0001 [
0002 {
0003 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
0004 "CollectPEBSRecord": "2",
0005 "Counter": "0,1,2,3,4,5",
0006 "EventCode": "0x34",
0007 "EventName": "MEM_BOUND_STALLS.IFETCH",
0008 "PEBScounters": "0,1,2,3,4,5",
0009 "SampleAfterValue": "200003",
0010 "Speculative": "1",
0011 "UMask": "0x38",
0012 "Unit": "cpu_atom"
0013 },
0014 {
0015 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in DRAM or MMIO (Non-DRAM).",
0016 "CollectPEBSRecord": "2",
0017 "Counter": "0,1,2,3,4,5",
0018 "EventCode": "0x34",
0019 "EventName": "MEM_BOUND_STALLS.IFETCH_DRAM_HIT",
0020 "PEBScounters": "0,1,2,3,4,5",
0021 "SampleAfterValue": "200003",
0022 "Speculative": "1",
0023 "UMask": "0x20",
0024 "Unit": "cpu_atom"
0025 },
0026 {
0027 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
0028 "CollectPEBSRecord": "2",
0029 "Counter": "0,1,2,3,4,5",
0030 "EventCode": "0x34",
0031 "EventName": "MEM_BOUND_STALLS.IFETCH_L2_HIT",
0032 "PEBScounters": "0,1,2,3,4,5",
0033 "SampleAfterValue": "200003",
0034 "Speculative": "1",
0035 "UMask": "0x8",
0036 "Unit": "cpu_atom"
0037 },
0038 {
0039 "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the LLC or other core with HITE/F/M.",
0040 "CollectPEBSRecord": "2",
0041 "Counter": "0,1,2,3,4,5",
0042 "EventCode": "0x34",
0043 "EventName": "MEM_BOUND_STALLS.IFETCH_LLC_HIT",
0044 "PEBScounters": "0,1,2,3,4,5",
0045 "SampleAfterValue": "200003",
0046 "Speculative": "1",
0047 "UMask": "0x10",
0048 "Unit": "cpu_atom"
0049 },
0050 {
0051 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in the L2, LLC, DRAM or MMIO (Non-DRAM).",
0052 "CollectPEBSRecord": "2",
0053 "Counter": "0,1,2,3,4,5",
0054 "EventCode": "0x34",
0055 "EventName": "MEM_BOUND_STALLS.LOAD",
0056 "PEBScounters": "0,1,2,3,4,5",
0057 "SampleAfterValue": "200003",
0058 "Speculative": "1",
0059 "UMask": "0x7",
0060 "Unit": "cpu_atom"
0061 },
0062 {
0063 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load miss which hit in DRAM or MMIO (Non-DRAM).",
0064 "CollectPEBSRecord": "2",
0065 "Counter": "0,1,2,3,4,5",
0066 "EventCode": "0x34",
0067 "EventName": "MEM_BOUND_STALLS.LOAD_DRAM_HIT",
0068 "PEBScounters": "0,1,2,3,4,5",
0069 "SampleAfterValue": "200003",
0070 "Speculative": "1",
0071 "UMask": "0x4",
0072 "Unit": "cpu_atom"
0073 },
0074 {
0075 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
0076 "CollectPEBSRecord": "2",
0077 "Counter": "0,1,2,3,4,5",
0078 "EventCode": "0x34",
0079 "EventName": "MEM_BOUND_STALLS.LOAD_L2_HIT",
0080 "PEBScounters": "0,1,2,3,4,5",
0081 "SampleAfterValue": "200003",
0082 "Speculative": "1",
0083 "UMask": "0x1",
0084 "Unit": "cpu_atom"
0085 },
0086 {
0087 "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the LLC or other core with HITE/F/M.",
0088 "CollectPEBSRecord": "2",
0089 "Counter": "0,1,2,3,4,5",
0090 "EventCode": "0x34",
0091 "EventName": "MEM_BOUND_STALLS.LOAD_LLC_HIT",
0092 "PEBScounters": "0,1,2,3,4,5",
0093 "SampleAfterValue": "200003",
0094 "Speculative": "1",
0095 "UMask": "0x2",
0096 "Unit": "cpu_atom"
0097 },
0098 {
0099 "BriefDescription": "Counts the number of load uops retired that hit in DRAM.",
0100 "CollectPEBSRecord": "2",
0101 "Counter": "0,1,2,3,4,5",
0102 "Data_LA": "1",
0103 "EventCode": "0xd1",
0104 "EventName": "MEM_LOAD_UOPS_RETIRED.DRAM_HIT",
0105 "PEBS": "1",
0106 "PEBScounters": "0,1,2,3,4,5",
0107 "SampleAfterValue": "200003",
0108 "UMask": "0x80",
0109 "Unit": "cpu_atom"
0110 },
0111 {
0112 "BriefDescription": "Counts the number of load uops retired that hit in the L2 cache.",
0113 "CollectPEBSRecord": "2",
0114 "Counter": "0,1,2,3,4,5",
0115 "Data_LA": "1",
0116 "EventCode": "0xd1",
0117 "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
0118 "PEBS": "1",
0119 "PEBScounters": "0,1,2,3,4,5",
0120 "SampleAfterValue": "200003",
0121 "UMask": "0x2",
0122 "Unit": "cpu_atom"
0123 },
0124 {
0125 "BriefDescription": "Counts the number of load uops retired that hit in the L3 cache.",
0126 "CollectPEBSRecord": "2",
0127 "Counter": "0,1,2,3,4,5",
0128 "Data_LA": "1",
0129 "EventCode": "0xd1",
0130 "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
0131 "PEBS": "1",
0132 "PEBScounters": "0,1,2,3,4,5",
0133 "SampleAfterValue": "200003",
0134 "UMask": "0x4",
0135 "Unit": "cpu_atom"
0136 },
0137 {
0138 "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons: load buffer, store buffer or RSV full.",
0139 "CollectPEBSRecord": "2",
0140 "Counter": "0,1,2,3,4,5",
0141 "EventCode": "0x04",
0142 "EventName": "MEM_SCHEDULER_BLOCK.ALL",
0143 "PEBScounters": "0,1,2,3,4,5",
0144 "SampleAfterValue": "20003",
0145 "Speculative": "1",
0146 "UMask": "0x7",
0147 "Unit": "cpu_atom"
0148 },
0149 {
0150 "BriefDescription": "Counts the number of cycles that uops are blocked due to a load buffer full condition.",
0151 "CollectPEBSRecord": "2",
0152 "Counter": "0,1,2,3,4,5",
0153 "EventCode": "0x04",
0154 "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
0155 "PEBScounters": "0,1,2,3,4,5",
0156 "SampleAfterValue": "20003",
0157 "Speculative": "1",
0158 "UMask": "0x2",
0159 "Unit": "cpu_atom"
0160 },
0161 {
0162 "BriefDescription": "Counts the number of cycles that uops are blocked due to an RSV full condition.",
0163 "CollectPEBSRecord": "2",
0164 "Counter": "0,1,2,3,4,5",
0165 "EventCode": "0x04",
0166 "EventName": "MEM_SCHEDULER_BLOCK.RSV",
0167 "PEBScounters": "0,1,2,3,4,5",
0168 "SampleAfterValue": "20003",
0169 "Speculative": "1",
0170 "UMask": "0x4",
0171 "Unit": "cpu_atom"
0172 },
0173 {
0174 "BriefDescription": "Counts the number of cycles that uops are blocked due to a store buffer full condition.",
0175 "CollectPEBSRecord": "2",
0176 "Counter": "0,1,2,3,4,5",
0177 "EventCode": "0x04",
0178 "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
0179 "PEBScounters": "0,1,2,3,4,5",
0180 "SampleAfterValue": "20003",
0181 "Speculative": "1",
0182 "UMask": "0x1",
0183 "Unit": "cpu_atom"
0184 },
0185 {
0186 "BriefDescription": "Counts the number of load uops retired.",
0187 "CollectPEBSRecord": "2",
0188 "Counter": "0,1,2,3,4,5",
0189 "Data_LA": "1",
0190 "EventCode": "0xd0",
0191 "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
0192 "PEBS": "1",
0193 "PEBScounters": "0,1,2,3,4,5",
0194 "SampleAfterValue": "200003",
0195 "UMask": "0x81",
0196 "Unit": "cpu_atom"
0197 },
0198 {
0199 "BriefDescription": "Counts the number of store uops retired.",
0200 "CollectPEBSRecord": "2",
0201 "Counter": "0,1,2,3,4,5",
0202 "Data_LA": "1",
0203 "EventCode": "0xd0",
0204 "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
0205 "PEBS": "1",
0206 "PEBScounters": "0,1,2,3,4,5",
0207 "SampleAfterValue": "200003",
0208 "UMask": "0x82",
0209 "Unit": "cpu_atom"
0210 },
0211 {
0212 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 128 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
0213 "CollectPEBSRecord": "3",
0214 "Counter": "0,1,2,3,4,5",
0215 "Data_LA": "1",
0216 "EventCode": "0xd0",
0217 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
0218 "L1_Hit_Indication": "1",
0219 "MSRIndex": "0x3F6",
0220 "MSRValue": "0x80",
0221 "PEBS": "2",
0222 "PEBScounters": "0,1,2,3,4,5",
0223 "SampleAfterValue": "1000003",
0224 "TakenAlone": "1",
0225 "UMask": "0x5",
0226 "Unit": "cpu_atom"
0227 },
0228 {
0229 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 16 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
0230 "CollectPEBSRecord": "3",
0231 "Counter": "0,1,2,3,4,5",
0232 "Data_LA": "1",
0233 "EventCode": "0xd0",
0234 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
0235 "L1_Hit_Indication": "1",
0236 "MSRIndex": "0x3F6",
0237 "MSRValue": "0x10",
0238 "PEBS": "2",
0239 "PEBScounters": "0,1,2,3,4,5",
0240 "SampleAfterValue": "1000003",
0241 "TakenAlone": "1",
0242 "UMask": "0x5",
0243 "Unit": "cpu_atom"
0244 },
0245 {
0246 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 256 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
0247 "CollectPEBSRecord": "3",
0248 "Counter": "0,1,2,3,4,5",
0249 "Data_LA": "1",
0250 "EventCode": "0xd0",
0251 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
0252 "L1_Hit_Indication": "1",
0253 "MSRIndex": "0x3F6",
0254 "MSRValue": "0x100",
0255 "PEBS": "2",
0256 "PEBScounters": "0,1,2,3,4,5",
0257 "SampleAfterValue": "1000003",
0258 "TakenAlone": "1",
0259 "UMask": "0x5",
0260 "Unit": "cpu_atom"
0261 },
0262 {
0263 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 32 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
0264 "CollectPEBSRecord": "3",
0265 "Counter": "0,1,2,3,4,5",
0266 "Data_LA": "1",
0267 "EventCode": "0xd0",
0268 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
0269 "L1_Hit_Indication": "1",
0270 "MSRIndex": "0x3F6",
0271 "MSRValue": "0x20",
0272 "PEBS": "2",
0273 "PEBScounters": "0,1,2,3,4,5",
0274 "SampleAfterValue": "1000003",
0275 "TakenAlone": "1",
0276 "UMask": "0x5",
0277 "Unit": "cpu_atom"
0278 },
0279 {
0280 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 4 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
0281 "CollectPEBSRecord": "3",
0282 "Counter": "0,1,2,3,4,5",
0283 "Data_LA": "1",
0284 "EventCode": "0xd0",
0285 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
0286 "L1_Hit_Indication": "1",
0287 "MSRIndex": "0x3F6",
0288 "MSRValue": "0x4",
0289 "PEBS": "2",
0290 "PEBScounters": "0,1,2,3,4,5",
0291 "SampleAfterValue": "1000003",
0292 "TakenAlone": "1",
0293 "UMask": "0x5",
0294 "Unit": "cpu_atom"
0295 },
0296 {
0297 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 512 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
0298 "CollectPEBSRecord": "3",
0299 "Counter": "0,1,2,3,4,5",
0300 "Data_LA": "1",
0301 "EventCode": "0xd0",
0302 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
0303 "L1_Hit_Indication": "1",
0304 "MSRIndex": "0x3F6",
0305 "MSRValue": "0x200",
0306 "PEBS": "2",
0307 "PEBScounters": "0,1,2,3,4,5",
0308 "SampleAfterValue": "1000003",
0309 "TakenAlone": "1",
0310 "UMask": "0x5",
0311 "Unit": "cpu_atom"
0312 },
0313 {
0314 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 64 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
0315 "CollectPEBSRecord": "3",
0316 "Counter": "0,1,2,3,4,5",
0317 "Data_LA": "1",
0318 "EventCode": "0xd0",
0319 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
0320 "L1_Hit_Indication": "1",
0321 "MSRIndex": "0x3F6",
0322 "MSRValue": "0x40",
0323 "PEBS": "2",
0324 "PEBScounters": "0,1,2,3,4,5",
0325 "SampleAfterValue": "1000003",
0326 "TakenAlone": "1",
0327 "UMask": "0x5",
0328 "Unit": "cpu_atom"
0329 },
0330 {
0331 "BriefDescription": "Counts the number of tagged loads with an instruction latency that exceeds or equals the threshold of 8 cycles as defined in MEC_CR_PEBS_LD_LAT_THRESHOLD (3F6H). Only counts with PEBS enabled.",
0332 "CollectPEBSRecord": "3",
0333 "Counter": "0,1,2,3,4,5",
0334 "Data_LA": "1",
0335 "EventCode": "0xd0",
0336 "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
0337 "L1_Hit_Indication": "1",
0338 "MSRIndex": "0x3F6",
0339 "MSRValue": "0x8",
0340 "PEBS": "2",
0341 "PEBScounters": "0,1,2,3,4,5",
0342 "SampleAfterValue": "1000003",
0343 "TakenAlone": "1",
0344 "UMask": "0x5",
0345 "Unit": "cpu_atom"
0346 },
0347 {
0348 "BriefDescription": "Counts the number of retired split load uops.",
0349 "CollectPEBSRecord": "2",
0350 "Counter": "0,1,2,3,4,5",
0351 "Data_LA": "1",
0352 "EventCode": "0xd0",
0353 "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
0354 "PEBS": "1",
0355 "PEBScounters": "0,1,2,3,4,5",
0356 "SampleAfterValue": "200003",
0357 "UMask": "0x41",
0358 "Unit": "cpu_atom"
0359 },
0360 {
0361 "BriefDescription": "Counts the number of stores uops retired. Counts with or without PEBS enabled.",
0362 "CollectPEBSRecord": "3",
0363 "Counter": "0,1,2,3,4,5",
0364 "Data_LA": "1",
0365 "EventCode": "0xd0",
0366 "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
0367 "L1_Hit_Indication": "1",
0368 "PEBS": "2",
0369 "PEBScounters": "0,1,2,3,4,5",
0370 "SampleAfterValue": "1000003",
0371 "UMask": "0x6",
0372 "Unit": "cpu_atom"
0373 },
0374 {
0375 "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop was sent, the snoop hit, and modified data was forwarded.",
0376 "Counter": "0,1,2,3,4,5",
0377 "EventCode": "0xB7",
0378 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
0379 "MSRIndex": "0x1a6,0x1a7",
0380 "MSRValue": "0x10003C0002",
0381 "SampleAfterValue": "100003",
0382 "UMask": "0x1",
0383 "Unit": "cpu_atom"
0384 },
0385 {
0386 "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to instruction cache misses.",
0387 "CollectPEBSRecord": "2",
0388 "Counter": "0,1,2,3,4,5",
0389 "EventCode": "0x71",
0390 "EventName": "TOPDOWN_FE_BOUND.ICACHE",
0391 "PEBScounters": "0,1,2,3,4,5",
0392 "SampleAfterValue": "1000003",
0393 "Speculative": "1",
0394 "UMask": "0x20",
0395 "Unit": "cpu_atom"
0396 },
0397 {
0398 "BriefDescription": "L1D.HWPF_MISS",
0399 "CollectPEBSRecord": "2",
0400 "Counter": "0,1,2,3",
0401 "EventCode": "0x51",
0402 "EventName": "L1D.HWPF_MISS",
0403 "PEBScounters": "0,1,2,3",
0404 "SampleAfterValue": "1000003",
0405 "Speculative": "1",
0406 "UMask": "0x20",
0407 "Unit": "cpu_core"
0408 },
0409 {
0410 "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
0411 "CollectPEBSRecord": "2",
0412 "Counter": "0,1,2,3",
0413 "EventCode": "0x51",
0414 "EventName": "L1D.REPLACEMENT",
0415 "PEBScounters": "0,1,2,3",
0416 "SampleAfterValue": "100003",
0417 "Speculative": "1",
0418 "UMask": "0x1",
0419 "Unit": "cpu_core"
0420 },
0421 {
0422 "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
0423 "CollectPEBSRecord": "2",
0424 "Counter": "0,1,2,3",
0425 "EventCode": "0x48",
0426 "EventName": "L1D_PEND_MISS.FB_FULL",
0427 "PEBScounters": "0,1,2,3",
0428 "SampleAfterValue": "1000003",
0429 "Speculative": "1",
0430 "UMask": "0x2",
0431 "Unit": "cpu_core"
0432 },
0433 {
0434 "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailablability.",
0435 "CollectPEBSRecord": "2",
0436 "Counter": "0,1,2,3",
0437 "CounterMask": "1",
0438 "EdgeDetect": "1",
0439 "EventCode": "0x48",
0440 "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
0441 "PEBScounters": "0,1,2,3",
0442 "SampleAfterValue": "1000003",
0443 "Speculative": "1",
0444 "UMask": "0x2",
0445 "Unit": "cpu_core"
0446 },
0447 {
0448 "BriefDescription": "This event is deprecated. Refer to new event L1D_PEND_MISS.L2_STALLS",
0449 "CollectPEBSRecord": "2",
0450 "Counter": "0,1,2,3",
0451 "EventCode": "0x48",
0452 "EventName": "L1D_PEND_MISS.L2_STALL",
0453 "PEBScounters": "0,1,2,3",
0454 "SampleAfterValue": "1000003",
0455 "Speculative": "1",
0456 "UMask": "0x4",
0457 "Unit": "cpu_core"
0458 },
0459 {
0460 "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
0461 "CollectPEBSRecord": "2",
0462 "Counter": "0,1,2,3",
0463 "EventCode": "0x48",
0464 "EventName": "L1D_PEND_MISS.L2_STALLS",
0465 "PEBScounters": "0,1,2,3",
0466 "SampleAfterValue": "1000003",
0467 "Speculative": "1",
0468 "UMask": "0x4",
0469 "Unit": "cpu_core"
0470 },
0471 {
0472 "BriefDescription": "Number of L1D misses that are outstanding",
0473 "CollectPEBSRecord": "2",
0474 "Counter": "0,1,2,3",
0475 "EventCode": "0x48",
0476 "EventName": "L1D_PEND_MISS.PENDING",
0477 "PEBScounters": "0,1,2,3",
0478 "SampleAfterValue": "1000003",
0479 "Speculative": "1",
0480 "UMask": "0x1",
0481 "Unit": "cpu_core"
0482 },
0483 {
0484 "BriefDescription": "Cycles with L1D load Misses outstanding.",
0485 "CollectPEBSRecord": "2",
0486 "Counter": "0,1,2,3",
0487 "CounterMask": "1",
0488 "EventCode": "0x48",
0489 "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
0490 "PEBScounters": "0,1,2,3",
0491 "SampleAfterValue": "1000003",
0492 "Speculative": "1",
0493 "UMask": "0x1",
0494 "Unit": "cpu_core"
0495 },
0496 {
0497 "BriefDescription": "L2 cache lines filling L2",
0498 "CollectPEBSRecord": "2",
0499 "Counter": "0,1,2,3",
0500 "EventCode": "0x25",
0501 "EventName": "L2_LINES_IN.ALL",
0502 "PEBScounters": "0,1,2,3",
0503 "SampleAfterValue": "100003",
0504 "Speculative": "1",
0505 "UMask": "0x1f",
0506 "Unit": "cpu_core"
0507 },
0508 {
0509 "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
0510 "CollectPEBSRecord": "2",
0511 "Counter": "0,1,2,3",
0512 "EventCode": "0x26",
0513 "EventName": "L2_LINES_OUT.USELESS_HWPF",
0514 "PEBScounters": "0,1,2,3",
0515 "SampleAfterValue": "200003",
0516 "Speculative": "1",
0517 "UMask": "0x4",
0518 "Unit": "cpu_core"
0519 },
0520 {
0521 "BriefDescription": "All accesses to L2 cache[This event is alias to L2_RQSTS.REFERENCES]",
0522 "CollectPEBSRecord": "2",
0523 "Counter": "0,1,2,3",
0524 "EventCode": "0x24",
0525 "EventName": "L2_REQUEST.ALL",
0526 "PEBScounters": "0,1,2,3",
0527 "SampleAfterValue": "200003",
0528 "Speculative": "1",
0529 "UMask": "0xff",
0530 "Unit": "cpu_core"
0531 },
0532 {
0533 "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_RQSTS.MISS]",
0534 "CollectPEBSRecord": "2",
0535 "Counter": "0,1,2,3",
0536 "EventCode": "0x24",
0537 "EventName": "L2_REQUEST.MISS",
0538 "PEBScounters": "0,1,2,3",
0539 "SampleAfterValue": "200003",
0540 "Speculative": "1",
0541 "UMask": "0x3f",
0542 "Unit": "cpu_core"
0543 },
0544 {
0545 "BriefDescription": "L2 code requests",
0546 "CollectPEBSRecord": "2",
0547 "Counter": "0,1,2,3",
0548 "EventCode": "0x24",
0549 "EventName": "L2_RQSTS.ALL_CODE_RD",
0550 "PEBScounters": "0,1,2,3",
0551 "SampleAfterValue": "200003",
0552 "Speculative": "1",
0553 "UMask": "0xe4",
0554 "Unit": "cpu_core"
0555 },
0556 {
0557 "BriefDescription": "Demand Data Read access L2 cache",
0558 "CollectPEBSRecord": "2",
0559 "Counter": "0,1,2,3",
0560 "EventCode": "0x24",
0561 "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
0562 "PEBScounters": "0,1,2,3",
0563 "SampleAfterValue": "200003",
0564 "Speculative": "1",
0565 "UMask": "0xe1",
0566 "Unit": "cpu_core"
0567 },
0568 {
0569 "BriefDescription": "Demand requests that miss L2 cache",
0570 "CollectPEBSRecord": "2",
0571 "Counter": "0,1,2,3",
0572 "EventCode": "0x24",
0573 "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
0574 "PEBScounters": "0,1,2,3",
0575 "SampleAfterValue": "200003",
0576 "Speculative": "1",
0577 "UMask": "0x27",
0578 "Unit": "cpu_core"
0579 },
0580 {
0581 "BriefDescription": "L2_RQSTS.ALL_HWPF",
0582 "CollectPEBSRecord": "2",
0583 "Counter": "0,1,2,3",
0584 "EventCode": "0x24",
0585 "EventName": "L2_RQSTS.ALL_HWPF",
0586 "PEBScounters": "0,1,2,3",
0587 "SampleAfterValue": "200003",
0588 "Speculative": "1",
0589 "UMask": "0xf0",
0590 "Unit": "cpu_core"
0591 },
0592 {
0593 "BriefDescription": "RFO requests to L2 cache.",
0594 "CollectPEBSRecord": "2",
0595 "Counter": "0,1,2,3",
0596 "EventCode": "0x24",
0597 "EventName": "L2_RQSTS.ALL_RFO",
0598 "PEBScounters": "0,1,2,3",
0599 "SampleAfterValue": "200003",
0600 "Speculative": "1",
0601 "UMask": "0xe2",
0602 "Unit": "cpu_core"
0603 },
0604 {
0605 "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
0606 "CollectPEBSRecord": "2",
0607 "Counter": "0,1,2,3",
0608 "EventCode": "0x24",
0609 "EventName": "L2_RQSTS.CODE_RD_HIT",
0610 "PEBScounters": "0,1,2,3",
0611 "SampleAfterValue": "200003",
0612 "Speculative": "1",
0613 "UMask": "0xc4",
0614 "Unit": "cpu_core"
0615 },
0616 {
0617 "BriefDescription": "L2 cache misses when fetching instructions",
0618 "CollectPEBSRecord": "2",
0619 "Counter": "0,1,2,3",
0620 "EventCode": "0x24",
0621 "EventName": "L2_RQSTS.CODE_RD_MISS",
0622 "PEBScounters": "0,1,2,3",
0623 "SampleAfterValue": "200003",
0624 "Speculative": "1",
0625 "UMask": "0x24",
0626 "Unit": "cpu_core"
0627 },
0628 {
0629 "BriefDescription": "Demand Data Read requests that hit L2 cache",
0630 "CollectPEBSRecord": "2",
0631 "Counter": "0,1,2,3",
0632 "EventCode": "0x24",
0633 "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
0634 "PEBScounters": "0,1,2,3",
0635 "SampleAfterValue": "200003",
0636 "Speculative": "1",
0637 "UMask": "0xc1",
0638 "Unit": "cpu_core"
0639 },
0640 {
0641 "BriefDescription": "Demand Data Read miss L2 cache",
0642 "CollectPEBSRecord": "2",
0643 "Counter": "0,1,2,3",
0644 "EventCode": "0x24",
0645 "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
0646 "PEBScounters": "0,1,2,3",
0647 "SampleAfterValue": "200003",
0648 "Speculative": "1",
0649 "UMask": "0x21",
0650 "Unit": "cpu_core"
0651 },
0652 {
0653 "BriefDescription": "L2_RQSTS.HWPF_MISS",
0654 "CollectPEBSRecord": "2",
0655 "Counter": "0,1,2,3",
0656 "EventCode": "0x24",
0657 "EventName": "L2_RQSTS.HWPF_MISS",
0658 "PEBScounters": "0,1,2,3",
0659 "SampleAfterValue": "200003",
0660 "Speculative": "1",
0661 "UMask": "0x30",
0662 "Unit": "cpu_core"
0663 },
0664 {
0665 "BriefDescription": "Read requests with true-miss in L2 cache.[This event is alias to L2_REQUEST.MISS]",
0666 "CollectPEBSRecord": "2",
0667 "Counter": "0,1,2,3",
0668 "EventCode": "0x24",
0669 "EventName": "L2_RQSTS.MISS",
0670 "PEBScounters": "0,1,2,3",
0671 "SampleAfterValue": "200003",
0672 "Speculative": "1",
0673 "UMask": "0x3f",
0674 "Unit": "cpu_core"
0675 },
0676 {
0677 "BriefDescription": "All accesses to L2 cache[This event is alias to L2_REQUEST.ALL]",
0678 "CollectPEBSRecord": "2",
0679 "Counter": "0,1,2,3",
0680 "EventCode": "0x24",
0681 "EventName": "L2_RQSTS.REFERENCES",
0682 "PEBScounters": "0,1,2,3",
0683 "SampleAfterValue": "200003",
0684 "Speculative": "1",
0685 "UMask": "0xff",
0686 "Unit": "cpu_core"
0687 },
0688 {
0689 "BriefDescription": "RFO requests that hit L2 cache.",
0690 "CollectPEBSRecord": "2",
0691 "Counter": "0,1,2,3",
0692 "EventCode": "0x24",
0693 "EventName": "L2_RQSTS.RFO_HIT",
0694 "PEBScounters": "0,1,2,3",
0695 "SampleAfterValue": "200003",
0696 "Speculative": "1",
0697 "UMask": "0xc2",
0698 "Unit": "cpu_core"
0699 },
0700 {
0701 "BriefDescription": "RFO requests that miss L2 cache",
0702 "CollectPEBSRecord": "2",
0703 "Counter": "0,1,2,3",
0704 "EventCode": "0x24",
0705 "EventName": "L2_RQSTS.RFO_MISS",
0706 "PEBScounters": "0,1,2,3",
0707 "SampleAfterValue": "200003",
0708 "Speculative": "1",
0709 "UMask": "0x22",
0710 "Unit": "cpu_core"
0711 },
0712 {
0713 "BriefDescription": "SW prefetch requests that hit L2 cache.",
0714 "CollectPEBSRecord": "2",
0715 "Counter": "0,1,2,3",
0716 "EventCode": "0x24",
0717 "EventName": "L2_RQSTS.SWPF_HIT",
0718 "PEBScounters": "0,1,2,3",
0719 "SampleAfterValue": "200003",
0720 "Speculative": "1",
0721 "UMask": "0xc8",
0722 "Unit": "cpu_core"
0723 },
0724 {
0725 "BriefDescription": "SW prefetch requests that miss L2 cache.",
0726 "CollectPEBSRecord": "2",
0727 "Counter": "0,1,2,3",
0728 "EventCode": "0x24",
0729 "EventName": "L2_RQSTS.SWPF_MISS",
0730 "PEBScounters": "0,1,2,3",
0731 "SampleAfterValue": "200003",
0732 "Speculative": "1",
0733 "UMask": "0x28",
0734 "Unit": "cpu_core"
0735 },
0736 {
0737 "BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
0738 "CollectPEBSRecord": "2",
0739 "Counter": "0,1,2,3,4,5,6,7",
0740 "EventCode": "0x2e",
0741 "EventName": "LONGEST_LAT_CACHE.MISS",
0742 "PEBScounters": "0,1,2,3,4,5,6,7",
0743 "SampleAfterValue": "100003",
0744 "Speculative": "1",
0745 "UMask": "0x41",
0746 "Unit": "cpu_core"
0747 },
0748 {
0749 "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
0750 "CollectPEBSRecord": "2",
0751 "Counter": "0,1,2,3,4,5,6,7",
0752 "EventCode": "0x2e",
0753 "EventName": "LONGEST_LAT_CACHE.REFERENCE",
0754 "PEBScounters": "0,1,2,3,4,5,6,7",
0755 "SampleAfterValue": "100003",
0756 "Speculative": "1",
0757 "UMask": "0x4f",
0758 "Unit": "cpu_core"
0759 },
0760 {
0761 "BriefDescription": "Retired load instructions.",
0762 "CollectPEBSRecord": "2",
0763 "Counter": "0,1,2,3",
0764 "Data_LA": "1",
0765 "EventCode": "0xd0",
0766 "EventName": "MEM_INST_RETIRED.ALL_LOADS",
0767 "PEBS": "1",
0768 "PEBScounters": "0,1,2,3",
0769 "SampleAfterValue": "1000003",
0770 "UMask": "0x81",
0771 "Unit": "cpu_core"
0772 },
0773 {
0774 "BriefDescription": "Retired store instructions.",
0775 "CollectPEBSRecord": "2",
0776 "Counter": "0,1,2,3",
0777 "Data_LA": "1",
0778 "EventCode": "0xd0",
0779 "EventName": "MEM_INST_RETIRED.ALL_STORES",
0780 "L1_Hit_Indication": "1",
0781 "PEBS": "1",
0782 "PEBScounters": "0,1,2,3",
0783 "SampleAfterValue": "1000003",
0784 "UMask": "0x82",
0785 "Unit": "cpu_core"
0786 },
0787 {
0788 "BriefDescription": "All retired memory instructions.",
0789 "CollectPEBSRecord": "2",
0790 "Counter": "0,1,2,3",
0791 "Data_LA": "1",
0792 "EventCode": "0xd0",
0793 "EventName": "MEM_INST_RETIRED.ANY",
0794 "L1_Hit_Indication": "1",
0795 "PEBS": "1",
0796 "PEBScounters": "0,1,2,3",
0797 "SampleAfterValue": "1000003",
0798 "UMask": "0x83",
0799 "Unit": "cpu_core"
0800 },
0801 {
0802 "BriefDescription": "Retired load instructions with locked access.",
0803 "CollectPEBSRecord": "2",
0804 "Counter": "0,1,2,3",
0805 "Data_LA": "1",
0806 "EventCode": "0xd0",
0807 "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
0808 "PEBS": "1",
0809 "PEBScounters": "0,1,2,3",
0810 "SampleAfterValue": "100007",
0811 "UMask": "0x21",
0812 "Unit": "cpu_core"
0813 },
0814 {
0815 "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
0816 "CollectPEBSRecord": "2",
0817 "Counter": "0,1,2,3",
0818 "Data_LA": "1",
0819 "EventCode": "0xd0",
0820 "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
0821 "PEBS": "1",
0822 "PEBScounters": "0,1,2,3",
0823 "SampleAfterValue": "100003",
0824 "UMask": "0x41",
0825 "Unit": "cpu_core"
0826 },
0827 {
0828 "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
0829 "CollectPEBSRecord": "2",
0830 "Counter": "0,1,2,3",
0831 "Data_LA": "1",
0832 "EventCode": "0xd0",
0833 "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
0834 "L1_Hit_Indication": "1",
0835 "PEBS": "1",
0836 "PEBScounters": "0,1,2,3",
0837 "SampleAfterValue": "100003",
0838 "UMask": "0x42",
0839 "Unit": "cpu_core"
0840 },
0841 {
0842 "BriefDescription": "Retired load instructions that miss the STLB.",
0843 "CollectPEBSRecord": "2",
0844 "Counter": "0,1,2,3",
0845 "Data_LA": "1",
0846 "EventCode": "0xd0",
0847 "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
0848 "PEBS": "1",
0849 "PEBScounters": "0,1,2,3",
0850 "SampleAfterValue": "100003",
0851 "UMask": "0x11",
0852 "Unit": "cpu_core"
0853 },
0854 {
0855 "BriefDescription": "Retired store instructions that miss the STLB.",
0856 "CollectPEBSRecord": "2",
0857 "Counter": "0,1,2,3",
0858 "Data_LA": "1",
0859 "EventCode": "0xd0",
0860 "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
0861 "L1_Hit_Indication": "1",
0862 "PEBS": "1",
0863 "PEBScounters": "0,1,2,3",
0864 "SampleAfterValue": "100003",
0865 "UMask": "0x12",
0866 "Unit": "cpu_core"
0867 },
0868 {
0869 "BriefDescription": "Completed demand load uops that miss the L1 d-cache.",
0870 "CollectPEBSRecord": "2",
0871 "Counter": "0,1,2,3",
0872 "EventCode": "0x43",
0873 "EventName": "MEM_LOAD_COMPLETED.L1_MISS_ANY",
0874 "PEBScounters": "0,1,2,3",
0875 "SampleAfterValue": "1000003",
0876 "Speculative": "1",
0877 "UMask": "0xfd",
0878 "Unit": "cpu_core"
0879 },
0880 {
0881 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
0882 "CollectPEBSRecord": "2",
0883 "Counter": "0,1,2,3",
0884 "Data_LA": "1",
0885 "EventCode": "0xd2",
0886 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
0887 "PEBS": "1",
0888 "PEBScounters": "0,1,2,3",
0889 "SampleAfterValue": "20011",
0890 "UMask": "0x4",
0891 "Unit": "cpu_core"
0892 },
0893 {
0894 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
0895 "CollectPEBSRecord": "2",
0896 "Counter": "0,1,2,3",
0897 "Data_LA": "1",
0898 "EventCode": "0xd2",
0899 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HIT",
0900 "PEBS": "1",
0901 "PEBScounters": "0,1,2,3",
0902 "SampleAfterValue": "20011",
0903 "UMask": "0x2",
0904 "Unit": "cpu_core"
0905 },
0906 {
0907 "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3",
0908 "CollectPEBSRecord": "2",
0909 "Counter": "0,1,2,3",
0910 "Data_LA": "1",
0911 "EventCode": "0xd2",
0912 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
0913 "PEBS": "1",
0914 "PEBScounters": "0,1,2,3",
0915 "SampleAfterValue": "20011",
0916 "UMask": "0x4",
0917 "Unit": "cpu_core"
0918 },
0919 {
0920 "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
0921 "CollectPEBSRecord": "2",
0922 "Counter": "0,1,2,3",
0923 "Data_LA": "1",
0924 "EventCode": "0xd2",
0925 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
0926 "PEBS": "1",
0927 "PEBScounters": "0,1,2,3",
0928 "SampleAfterValue": "20011",
0929 "UMask": "0x1",
0930 "Unit": "cpu_core"
0931 },
0932 {
0933 "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
0934 "CollectPEBSRecord": "2",
0935 "Counter": "0,1,2,3",
0936 "Data_LA": "1",
0937 "EventCode": "0xd2",
0938 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
0939 "PEBS": "1",
0940 "PEBScounters": "0,1,2,3",
0941 "SampleAfterValue": "100003",
0942 "UMask": "0x8",
0943 "Unit": "cpu_core"
0944 },
0945 {
0946 "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
0947 "CollectPEBSRecord": "2",
0948 "Counter": "0,1,2,3",
0949 "Data_LA": "1",
0950 "EventCode": "0xd2",
0951 "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
0952 "PEBS": "1",
0953 "PEBScounters": "0,1,2,3",
0954 "SampleAfterValue": "20011",
0955 "UMask": "0x2",
0956 "Unit": "cpu_core"
0957 },
0958 {
0959 "BriefDescription": "Retired load instructions which data sources missed L3 but serviced from local dram",
0960 "Counter": "0,1,2,3",
0961 "Data_LA": "1",
0962 "EventCode": "0xd3",
0963 "EventName": "MEM_LOAD_L3_MISS_RETIRED.LOCAL_DRAM",
0964 "PEBScounters": "0,1,2,3",
0965 "SampleAfterValue": "100007",
0966 "UMask": "0x1",
0967 "Unit": "cpu_core"
0968 },
0969 {
0970 "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
0971 "CollectPEBSRecord": "2",
0972 "Counter": "0,1,2,3",
0973 "Data_LA": "1",
0974 "EventCode": "0xd4",
0975 "EventName": "MEM_LOAD_MISC_RETIRED.UC",
0976 "PEBS": "1",
0977 "PEBScounters": "0,1,2,3",
0978 "SampleAfterValue": "100007",
0979 "UMask": "0x4",
0980 "Unit": "cpu_core"
0981 },
0982 {
0983 "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
0984 "CollectPEBSRecord": "2",
0985 "Counter": "0,1,2,3",
0986 "Data_LA": "1",
0987 "EventCode": "0xd1",
0988 "EventName": "MEM_LOAD_RETIRED.FB_HIT",
0989 "PEBS": "1",
0990 "PEBScounters": "0,1,2,3",
0991 "SampleAfterValue": "100007",
0992 "UMask": "0x40",
0993 "Unit": "cpu_core"
0994 },
0995 {
0996 "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
0997 "CollectPEBSRecord": "2",
0998 "Counter": "0,1,2,3",
0999 "Data_LA": "1",
1000 "EventCode": "0xd1",
1001 "EventName": "MEM_LOAD_RETIRED.L1_HIT",
1002 "PEBS": "1",
1003 "PEBScounters": "0,1,2,3",
1004 "SampleAfterValue": "1000003",
1005 "UMask": "0x1",
1006 "Unit": "cpu_core"
1007 },
1008 {
1009 "BriefDescription": "Retired load instructions missed L1 cache as data sources",
1010 "CollectPEBSRecord": "2",
1011 "Counter": "0,1,2,3",
1012 "Data_LA": "1",
1013 "EventCode": "0xd1",
1014 "EventName": "MEM_LOAD_RETIRED.L1_MISS",
1015 "PEBS": "1",
1016 "PEBScounters": "0,1,2,3",
1017 "SampleAfterValue": "200003",
1018 "UMask": "0x8",
1019 "Unit": "cpu_core"
1020 },
1021 {
1022 "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
1023 "CollectPEBSRecord": "2",
1024 "Counter": "0,1,2,3",
1025 "Data_LA": "1",
1026 "EventCode": "0xd1",
1027 "EventName": "MEM_LOAD_RETIRED.L2_HIT",
1028 "PEBS": "1",
1029 "PEBScounters": "0,1,2,3",
1030 "SampleAfterValue": "200003",
1031 "UMask": "0x2",
1032 "Unit": "cpu_core"
1033 },
1034 {
1035 "BriefDescription": "Retired load instructions missed L2 cache as data sources",
1036 "CollectPEBSRecord": "2",
1037 "Counter": "0,1,2,3",
1038 "Data_LA": "1",
1039 "EventCode": "0xd1",
1040 "EventName": "MEM_LOAD_RETIRED.L2_MISS",
1041 "PEBS": "1",
1042 "PEBScounters": "0,1,2,3",
1043 "SampleAfterValue": "100021",
1044 "UMask": "0x10",
1045 "Unit": "cpu_core"
1046 },
1047 {
1048 "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
1049 "CollectPEBSRecord": "2",
1050 "Counter": "0,1,2,3",
1051 "Data_LA": "1",
1052 "EventCode": "0xd1",
1053 "EventName": "MEM_LOAD_RETIRED.L3_HIT",
1054 "PEBS": "1",
1055 "PEBScounters": "0,1,2,3",
1056 "SampleAfterValue": "100021",
1057 "UMask": "0x4",
1058 "Unit": "cpu_core"
1059 },
1060 {
1061 "BriefDescription": "Retired load instructions missed L3 cache as data sources",
1062 "CollectPEBSRecord": "2",
1063 "Counter": "0,1,2,3",
1064 "Data_LA": "1",
1065 "EventCode": "0xd1",
1066 "EventName": "MEM_LOAD_RETIRED.L3_MISS",
1067 "PEBS": "1",
1068 "PEBScounters": "0,1,2,3",
1069 "SampleAfterValue": "50021",
1070 "UMask": "0x20",
1071 "Unit": "cpu_core"
1072 },
1073 {
1074 "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
1075 "CollectPEBSRecord": "2",
1076 "Counter": "0,1,2,3",
1077 "EventCode": "0x44",
1078 "EventName": "MEM_STORE_RETIRED.L2_HIT",
1079 "PEBScounters": "0,1,2,3",
1080 "SampleAfterValue": "200003",
1081 "UMask": "0x1",
1082 "Unit": "cpu_core"
1083 },
1084 {
1085 "BriefDescription": "Retired memory uops for any access",
1086 "Counter": "0,1,2,3,4,5,6,7",
1087 "EventCode": "0xe5",
1088 "EventName": "MEM_UOP_RETIRED.ANY",
1089 "PEBScounters": "0,1,2,3,4,5,6,7",
1090 "SampleAfterValue": "1000003",
1091 "UMask": "0x3",
1092 "Unit": "cpu_core"
1093 },
1094 {
1095 "BriefDescription": "Counts demand data reads that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
1096 "Counter": "0,1,2,3,4,5,6,7",
1097 "EventCode": "0x2A,0x2B",
1098 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
1099 "MSRIndex": "0x1a6,0x1a7",
1100 "MSRValue": "0x10003C0001",
1101 "SampleAfterValue": "100003",
1102 "UMask": "0x1",
1103 "Unit": "cpu_core"
1104 },
1105 {
1106 "BriefDescription": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
1107 "Counter": "0,1,2,3,4,5,6,7",
1108 "EventCode": "0x2A,0x2B",
1109 "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
1110 "MSRIndex": "0x1a6,0x1a7",
1111 "MSRValue": "0x8003C0001",
1112 "SampleAfterValue": "100003",
1113 "UMask": "0x1",
1114 "Unit": "cpu_core"
1115 },
1116 {
1117 "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that resulted in a snoop hit in another cores caches, data forwarding is required as the data is modified.",
1118 "Counter": "0,1,2,3,4,5,6,7",
1119 "EventCode": "0x2A,0x2B",
1120 "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
1121 "MSRIndex": "0x1a6,0x1a7",
1122 "MSRValue": "0x10003C0002",
1123 "SampleAfterValue": "100003",
1124 "UMask": "0x1",
1125 "Unit": "cpu_core"
1126 },
1127 {
1128 "BriefDescription": "OFFCORE_REQUESTS.ALL_REQUESTS",
1129 "CollectPEBSRecord": "2",
1130 "Counter": "0,1,2,3",
1131 "EventCode": "0x21",
1132 "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
1133 "PEBScounters": "0,1,2,3",
1134 "SampleAfterValue": "100003",
1135 "Speculative": "1",
1136 "UMask": "0x80",
1137 "Unit": "cpu_core"
1138 },
1139 {
1140 "BriefDescription": "Demand and prefetch data reads",
1141 "CollectPEBSRecord": "2",
1142 "Counter": "0,1,2,3",
1143 "EventCode": "0x21",
1144 "EventName": "OFFCORE_REQUESTS.DATA_RD",
1145 "PEBScounters": "0,1,2,3",
1146 "SampleAfterValue": "100003",
1147 "Speculative": "1",
1148 "UMask": "0x8",
1149 "Unit": "cpu_core"
1150 },
1151 {
1152 "BriefDescription": "Demand Data Read requests sent to uncore",
1153 "CollectPEBSRecord": "2",
1154 "Counter": "0,1,2,3",
1155 "EventCode": "0x21",
1156 "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
1157 "PEBScounters": "0,1,2,3",
1158 "SampleAfterValue": "100003",
1159 "Speculative": "1",
1160 "UMask": "0x1",
1161 "Unit": "cpu_core"
1162 },
1163 {
1164 "BriefDescription": "This event is deprecated. Refer to new event OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
1165 "CollectPEBSRecord": "2",
1166 "Counter": "0,1,2,3",
1167 "Errata": "ADL038",
1168 "EventCode": "0x20",
1169 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
1170 "PEBScounters": "0,1,2,3",
1171 "SampleAfterValue": "1000003",
1172 "Speculative": "1",
1173 "UMask": "0x8",
1174 "Unit": "cpu_core"
1175 },
1176 {
1177 "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
1178 "CollectPEBSRecord": "2",
1179 "Counter": "0,1,2,3",
1180 "CounterMask": "1",
1181 "Errata": "ADL038",
1182 "EventCode": "0x20",
1183 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
1184 "PEBScounters": "0,1,2,3",
1185 "SampleAfterValue": "1000003",
1186 "Speculative": "1",
1187 "UMask": "0x8",
1188 "Unit": "cpu_core"
1189 },
1190 {
1191 "BriefDescription": "For every cycle where the core is waiting on at least 1 outstanding Demand RFO request, increments by 1.",
1192 "CollectPEBSRecord": "2",
1193 "Counter": "0,1,2,3",
1194 "CounterMask": "1",
1195 "EventCode": "0x20",
1196 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
1197 "PEBScounters": "0,1,2,3",
1198 "SampleAfterValue": "1000003",
1199 "Speculative": "1",
1200 "UMask": "0x4",
1201 "Unit": "cpu_core"
1202 },
1203 {
1204 "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
1205 "CollectPEBSRecord": "2",
1206 "Counter": "0,1,2,3",
1207 "Errata": "ADL038",
1208 "EventCode": "0x20",
1209 "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
1210 "PEBScounters": "0,1,2,3",
1211 "SampleAfterValue": "1000003",
1212 "Speculative": "1",
1213 "UMask": "0x8",
1214 "Unit": "cpu_core"
1215 },
1216 {
1217 "BriefDescription": "Number of PREFETCHNTA instructions executed.",
1218 "CollectPEBSRecord": "2",
1219 "Counter": "0,1,2,3",
1220 "EventCode": "0x40",
1221 "EventName": "SW_PREFETCH_ACCESS.NTA",
1222 "PEBScounters": "0,1,2,3",
1223 "SampleAfterValue": "100003",
1224 "Speculative": "1",
1225 "UMask": "0x1",
1226 "Unit": "cpu_core"
1227 },
1228 {
1229 "BriefDescription": "Number of PREFETCHW instructions executed.",
1230 "CollectPEBSRecord": "2",
1231 "Counter": "0,1,2,3",
1232 "EventCode": "0x40",
1233 "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
1234 "PEBScounters": "0,1,2,3",
1235 "SampleAfterValue": "100003",
1236 "Speculative": "1",
1237 "UMask": "0x8",
1238 "Unit": "cpu_core"
1239 },
1240 {
1241 "BriefDescription": "Number of PREFETCHT0 instructions executed.",
1242 "CollectPEBSRecord": "2",
1243 "Counter": "0,1,2,3",
1244 "EventCode": "0x40",
1245 "EventName": "SW_PREFETCH_ACCESS.T0",
1246 "PEBScounters": "0,1,2,3",
1247 "SampleAfterValue": "100003",
1248 "Speculative": "1",
1249 "UMask": "0x2",
1250 "Unit": "cpu_core"
1251 },
1252 {
1253 "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
1254 "CollectPEBSRecord": "2",
1255 "Counter": "0,1,2,3",
1256 "EventCode": "0x40",
1257 "EventName": "SW_PREFETCH_ACCESS.T1_T2",
1258 "PEBScounters": "0,1,2,3",
1259 "SampleAfterValue": "100003",
1260 "Speculative": "1",
1261 "UMask": "0x4",
1262 "Unit": "cpu_core"
1263 }
1264 ]
