0001 [
0002 {
0003 "Unit": "CPU-M-CF",
0004 "EventCode": "128",
0005 "EventName": "L1D_L2_SOURCED_WRITES",
0006 "BriefDescription": "L1D L2 Sourced Writes",
0007 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from the Level-2 cache."
0008 },
0009 {
0010 "Unit": "CPU-M-CF",
0011 "EventCode": "129",
0012 "EventName": "L1I_L2_SOURCED_WRITES",
0013 "BriefDescription": "L1I L2 Sourced Writes",
0014 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 cache."
0015 },
0016 {
0017 "Unit": "CPU-M-CF",
0018 "EventCode": "130",
0019 "EventName": "DTLB1_MISSES",
0020 "BriefDescription": "DTLB1 Misses",
0021 "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
0022 },
0023 {
0024 "Unit": "CPU-M-CF",
0025 "EventCode": "131",
0026 "EventName": "ITLB1_MISSES",
0027 "BriefDescription": "ITLB1 Misses",
0028 "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle a ITLB1 miss is in progress."
0029 },
0030 {
0031 "Unit": "CPU-M-CF",
0032 "EventCode": "133",
0033 "EventName": "L2C_STORES_SENT",
0034 "BriefDescription": "L2C Stores Sent",
0035 "PublicDescription": "Incremented by one for every store sent to Level-2 cache."
0036 },
0037 {
0038 "Unit": "CPU-M-CF",
0039 "EventCode": "134",
0040 "EventName": "L1D_OFFBOOK_L3_SOURCED_WRITES",
0041 "BriefDescription": "L1D Off-Book L3 Sourced Writes",
0042 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-3 cache."
0043 },
0044 {
0045 "Unit": "CPU-M-CF",
0046 "EventCode": "135",
0047 "EventName": "L1D_ONBOOK_L4_SOURCED_WRITES",
0048 "BriefDescription": "L1D On-Book L4 Sourced Writes",
0049 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Book Level-4 cache."
0050 },
0051 {
0052 "Unit": "CPU-M-CF",
0053 "EventCode": "136",
0054 "EventName": "L1I_ONBOOK_L4_SOURCED_WRITES",
0055 "BriefDescription": "L1I On-Book L4 Sourced Writes",
0056 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Book Level-4 cache."
0057 },
0058 {
0059 "Unit": "CPU-M-CF",
0060 "EventCode": "137",
0061 "EventName": "L1D_RO_EXCL_WRITES",
0062 "BriefDescription": "L1D Read-only Exclusive Writes",
0063 "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
0064 },
0065 {
0066 "Unit": "CPU-M-CF",
0067 "EventCode": "138",
0068 "EventName": "L1D_OFFBOOK_L4_SOURCED_WRITES",
0069 "BriefDescription": "L1D Off-Book L4 Sourced Writes",
0070 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
0071 },
0072 {
0073 "Unit": "CPU-M-CF",
0074 "EventCode": "139",
0075 "EventName": "L1I_OFFBOOK_L4_SOURCED_WRITES",
0076 "BriefDescription": "L1I Off-Book L4 Sourced Writes",
0077 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Book Level-4 cache."
0078 },
0079 {
0080 "Unit": "CPU-M-CF",
0081 "EventCode": "140",
0082 "EventName": "DTLB1_HPAGE_WRITES",
0083 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
0084 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page."
0085 },
0086 {
0087 "Unit": "CPU-M-CF",
0088 "EventCode": "141",
0089 "EventName": "L1D_LMEM_SOURCED_WRITES",
0090 "BriefDescription": "L1D Local Memory Sourced Writes",
0091 "PublicDescription": "A directory write to the Level-1 Data Cache where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
0092 },
0093 {
0094 "Unit": "CPU-M-CF",
0095 "EventCode": "142",
0096 "EventName": "L1I_LMEM_SOURCED_WRITES",
0097 "BriefDescription": "L1I Local Memory Sourced Writes",
0098 "PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the same book as the Instruction cache (Local Memory)."
0099 },
0100 {
0101 "Unit": "CPU-M-CF",
0102 "EventCode": "143",
0103 "EventName": "L1I_OFFBOOK_L3_SOURCED_WRITES",
0104 "BriefDescription": "L1I Off-Book L3 Sourced Writes",
0105 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Book Level-3 cache."
0106 },
0107 {
0108 "Unit": "CPU-M-CF",
0109 "EventCode": "144",
0110 "EventName": "DTLB1_WRITES",
0111 "BriefDescription": "DTLB1 Writes",
0112 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
0113 },
0114 {
0115 "Unit": "CPU-M-CF",
0116 "EventCode": "145",
0117 "EventName": "ITLB1_WRITES",
0118 "BriefDescription": "ITLB1 Writes",
0119 "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
0120 },
0121 {
0122 "Unit": "CPU-M-CF",
0123 "EventCode": "146",
0124 "EventName": "TLB2_PTE_WRITES",
0125 "BriefDescription": "TLB2 PTE Writes",
0126 "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
0127 },
0128 {
0129 "Unit": "CPU-M-CF",
0130 "EventCode": "147",
0131 "EventName": "TLB2_CRSTE_HPAGE_WRITES",
0132 "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
0133 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation."
0134 },
0135 {
0136 "Unit": "CPU-M-CF",
0137 "EventCode": "148",
0138 "EventName": "TLB2_CRSTE_WRITES",
0139 "BriefDescription": "TLB2 CRSTE Writes",
0140 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays."
0141 },
0142 {
0143 "Unit": "CPU-M-CF",
0144 "EventCode": "150",
0145 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
0146 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
0147 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an On Chip Level-3 cache."
0148 },
0149 {
0150 "Unit": "CPU-M-CF",
0151 "EventCode": "152",
0152 "EventName": "L1D_OFFCHIP_L3_SOURCED_WRITES",
0153 "BriefDescription": "L1D Off-Chip L3 Sourced Writes",
0154 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache."
0155 },
0156 {
0157 "Unit": "CPU-M-CF",
0158 "EventCode": "153",
0159 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
0160 "BriefDescription": "L1I On-Chip L3 Sourced Writes",
0161 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an On Chip Level-3 cache."
0162 },
0163 {
0164 "Unit": "CPU-M-CF",
0165 "EventCode": "155",
0166 "EventName": "L1I_OFFCHIP_L3_SOURCED_WRITES",
0167 "BriefDescription": "L1I Off-Chip L3 Sourced Writes",
0168 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from an Off Chip/On Book Level-3 cache."
0169 }
0170 ]
