0001 [
0002 {
0003 "Unit": "CPU-M-CF",
0004 "EventCode": "128",
0005 "EventName": "L1D_RO_EXCL_WRITES",
0006 "BriefDescription": "L1D Read-only Exclusive Writes",
0007 "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
0008 },
0009 {
0010 "Unit": "CPU-M-CF",
0011 "EventCode": "129",
0012 "EventName": "DTLB2_WRITES",
0013 "BriefDescription": "DTLB2 Writes",
0014 "PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines."
0015 },
0016 {
0017 "Unit": "CPU-M-CF",
0018 "EventCode": "130",
0019 "EventName": "DTLB2_MISSES",
0020 "BriefDescription": "DTLB2 Misses",
0021 "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines."
0022 },
0023 {
0024 "Unit": "CPU-M-CF",
0025 "EventCode": "131",
0026 "EventName": "CRSTE_1MB_WRITES",
0027 "BriefDescription": "One Megabyte CRSTE writes",
0028 "PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page."
0029 },
0030 {
0031 "Unit": "CPU-M-CF",
0032 "EventCode": "132",
0033 "EventName": "DTLB2_GPAGE_WRITES",
0034 "BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
0035 "PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB."
0036 },
0037 {
0038 "Unit": "CPU-M-CF",
0039 "EventCode": "134",
0040 "EventName": "ITLB2_WRITES",
0041 "BriefDescription": "ITLB2 Writes",
0042 "PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines."
0043 },
0044 {
0045 "Unit": "CPU-M-CF",
0046 "EventCode": "135",
0047 "EventName": "ITLB2_MISSES",
0048 "BriefDescription": "ITLB2 Misses",
0049 "PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines."
0050 },
0051 {
0052 "Unit": "CPU-M-CF",
0053 "EventCode": "137",
0054 "EventName": "TLB2_PTE_WRITES",
0055 "BriefDescription": "TLB2 Page Table Entry Writes",
0056 "PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
0057 },
0058 {
0059 "Unit": "CPU-M-CF",
0060 "EventCode": "138",
0061 "EventName": "TLB2_CRSTE_WRITES",
0062 "BriefDescription": "TLB2 Combined Region and Segment Entry Writes",
0063 "PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
0064 },
0065 {
0066 "Unit": "CPU-M-CF",
0067 "EventCode": "139",
0068 "EventName": "TLB2_ENGINES_BUSY",
0069 "BriefDescription": "TLB2 Engines Busy",
0070 "PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
0071 },
0072 {
0073 "Unit": "CPU-M-CF",
0074 "EventCode": "140",
0075 "EventName": "TX_C_TEND",
0076 "BriefDescription": "Completed TEND instructions in constrained TX mode",
0077 "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
0078 },
0079 {
0080 "Unit": "CPU-M-CF",
0081 "EventCode": "141",
0082 "EventName": "TX_NC_TEND",
0083 "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
0084 "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
0085 },
0086 {
0087 "Unit": "CPU-M-CF",
0088 "EventCode": "143",
0089 "EventName": "L1C_TLB2_MISSES",
0090 "BriefDescription": "L1C TLB2 Misses",
0091 "PublicDescription": "Increments by one for any cycle where a level-1 cache or level-2 TLB miss is in progress."
0092 },
0093 {
0094 "Unit": "CPU-M-CF",
0095 "EventCode": "145",
0096 "EventName": "DCW_REQ",
0097 "BriefDescription": "Directory Write Level 1 Data Cache from Cache",
0098 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache."
0099 },
0100 {
0101 "Unit": "CPU-M-CF",
0102 "EventCode": "146",
0103 "EventName": "DCW_REQ_IV",
0104 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Intervention",
0105 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache with intervention."
0106 },
0107 {
0108 "Unit": "CPU-M-CF",
0109 "EventCode": "147",
0110 "EventName": "DCW_REQ_CHIP_HIT",
0111 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Chip HP Hit",
0112 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
0113 },
0114 {
0115 "Unit": "CPU-M-CF",
0116 "EventCode": "148",
0117 "EventName": "DCW_REQ_DRAWER_HIT",
0118 "BriefDescription": "Directory Write Level 1 Data Cache from Cache with Drawer HP Hit",
0119 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestor’s Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
0120 },
0121 {
0122 "Unit": "CPU-M-CF",
0123 "EventCode": "149",
0124 "EventName": "DCW_ON_CHIP",
0125 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache",
0126 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
0127 },
0128 {
0129 "Unit": "CPU-M-CF",
0130 "EventCode": "150",
0131 "EventName": "DCW_ON_CHIP_IV",
0132 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Intervention",
0133 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
0134 },
0135 {
0136 "Unit": "CPU-M-CF",
0137 "EventCode": "151",
0138 "EventName": "DCW_ON_CHIP_CHIP_HIT",
0139 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Chip HP Hit",
0140 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
0141 },
0142 {
0143 "Unit": "CPU-M-CF",
0144 "EventCode": "152",
0145 "EventName": "DCW_ON_CHIP_DRAWER_HIT",
0146 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Cache with Drawer HP Hit",
0147 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
0148 },
0149 {
0150 "Unit": "CPU-M-CF",
0151 "EventCode": "153",
0152 "EventName": "DCW_ON_MODULE",
0153 "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Cache",
0154 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
0155 },
0156 {
0157 "Unit": "CPU-M-CF",
0158 "EventCode": "154",
0159 "EventName": "DCW_ON_DRAWER",
0160 "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Cache",
0161 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
0162 },
0163 {
0164 "Unit": "CPU-M-CF",
0165 "EventCode": "155",
0166 "EventName": "DCW_OFF_DRAWER",
0167 "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Cache",
0168 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
0169 },
0170 {
0171 "Unit": "CPU-M-CF",
0172 "EventCode": "156",
0173 "EventName": "DCW_ON_CHIP_MEMORY",
0174 "BriefDescription": "Directory Write Level 1 Data Cache from On-Chip Memory",
0175 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory."
0176 },
0177 {
0178 "Unit": "CPU-M-CF",
0179 "EventCode": "157",
0180 "EventName": "DCW_ON_MODULE_MEMORY",
0181 "BriefDescription": "Directory Write Level 1 Data Cache from On-Module Memory",
0182 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Module memory."
0183 },
0184 {
0185 "Unit": "CPU-M-CF",
0186 "EventCode": "158",
0187 "EventName": "DCW_ON_DRAWER_MEMORY",
0188 "BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer Memory",
0189 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory."
0190 },
0191 {
0192 "Unit": "CPU-M-CF",
0193 "EventCode": "159",
0194 "EventName": "DCW_OFF_DRAWER_MEMORY",
0195 "BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer Memory",
0196 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory."
0197 },
0198 {
0199 "Unit": "CPU-M-CF",
0200 "EventCode": "160",
0201 "EventName": "IDCW_ON_MODULE_IV",
0202 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Intervention",
0203 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention."
0204 },
0205 {
0206 "Unit": "CPU-M-CF",
0207 "EventCode": "161",
0208 "EventName": "IDCW_ON_MODULE_CHIP_HIT",
0209 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Chip Hit",
0210 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using chip horizontal persistence, Chip-HP hit."
0211 },
0212 {
0213 "Unit": "CPU-M-CF",
0214 "EventCode": "162",
0215 "EventName": "IDCW_ON_MODULE_DRAWER_HIT",
0216 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory Cache with Drawer Hit",
0217 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
0218 },
0219 {
0220 "Unit": "CPU-M-CF",
0221 "EventCode": "163",
0222 "EventName": "IDCW_ON_DRAWER_IV",
0223 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Intervention",
0224 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention."
0225 },
0226 {
0227 "Unit": "CPU-M-CF",
0228 "EventCode": "164",
0229 "EventName": "IDCW_ON_DRAWER_CHIP_HIT",
0230 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Chip Hit",
0231 "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit."
0232 },
0233 {
0234 "Unit": "CPU-M-CF",
0235 "EventCode": "165",
0236 "EventName": "IDCW_ON_DRAWER_DRAWER_HIT",
0237 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer Cache with Drawer Hit",
0238 "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
0239 },
0240 {
0241 "Unit": "CPU-M-CF",
0242 "EventCode": "166",
0243 "EventName": "IDCW_OFF_DRAWER_IV",
0244 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Intervention",
0245 "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention."
0246 },
0247 {
0248 "Unit": "CPU-M-CF",
0249 "EventCode": "167",
0250 "EventName": "IDCW_OFF_DRAWER_CHIP_HIT",
0251 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Chip Hit",
0252 "PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using chip level horizontal persistence, Chip-HP hit."
0253 },
0254 {
0255 "Unit": "CPU-M-CF",
0256 "EventCode": "168",
0257 "EventName": "IDCW_OFF_DRAWER_DRAWER_HIT",
0258 "BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer Cache with Drawer Hit",
0259 "PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
0260 },
0261 {
0262 "Unit": "CPU-M-CF",
0263 "EventCode": "169",
0264 "EventName": "ICW_REQ",
0265 "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache",
0266 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache."
0267 },
0268 {
0269 "Unit": "CPU-M-CF",
0270 "EventCode": "170",
0271 "EventName": "ICW_REQ_IV",
0272 "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Intervention",
0273 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
0274 },
0275 {
0276 "Unit": "CPU-M-CF",
0277 "EventCode": "171",
0278 "EventName": "ICW_REQ_CHIP_HIT",
0279 "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Chip HP Hit",
0280 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache using chip level horizontal persistence, Chip-HP hit."
0281 },
0282 {
0283 "Unit": "CPU-M-CF",
0284 "EventCode": "172",
0285 "EventName": "ICW_REQ_DRAWER_HIT",
0286 "BriefDescription": "Directory Write Level 1 Instruction Cache from Cache with Drawer HP Hit",
0287 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestor’s Level-2 cache using drawer level horizontal persistence, Drawer-HP hit."
0288 },
0289 {
0290 "Unit": "CPU-M-CF",
0291 "EventCode": "173",
0292 "EventName": "ICW_ON_CHIP",
0293 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache",
0294 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
0295 },
0296 {
0297 "Unit": "CPU-M-CF",
0298 "EventCode": "174",
0299 "EventName": "ICW_ON_CHIP_IV",
0300 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Intervention",
0301 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Chip Level-2 cache with intervention."
0302 },
0303 {
0304 "Unit": "CPU-M-CF",
0305 "EventCode": "175",
0306 "EventName": "ICW_ON_CHIP_CHIP_HIT",
0307 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Chip HP Hit",
0308 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache using chip level horizontal persistence, Chip-HP hit."
0309 },
0310 {
0311 "Unit": "CPU-M-CF",
0312 "EventCode": "176",
0313 "EventName": "ICW_ON_CHIP_DRAWER_HIT",
0314 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Cache with Drawer HP Hit",
0315 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache using drawer level horizontal persistence, Drawer-HP hit."
0316 },
0317 {
0318 "Unit": "CPU-M-CF",
0319 "EventCode": "177",
0320 "EventName": "ICW_ON_MODULE",
0321 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Cache",
0322 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
0323 },
0324 {
0325 "Unit": "CPU-M-CF",
0326 "EventCode": "178",
0327 "EventName": "ICW_ON_DRAWER",
0328 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Cache",
0329 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an On-Drawer Level-2 cache."
0330 },
0331 {
0332 "Unit": "CPU-M-CF",
0333 "EventCode": "179",
0334 "EventName": "ICW_OFF_DRAWER",
0335 "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Cache",
0336 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced an Off-Drawer Level-2 cache."
0337 },
0338 {
0339 "Unit": "CPU-M-CF",
0340 "EventCode": "180",
0341 "EventName": "ICW_ON_CHIP_MEMORY",
0342 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip Memory",
0343 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
0344 },
0345 {
0346 "Unit": "CPU-M-CF",
0347 "EventCode": "181",
0348 "EventName": "ICW_ON_MODULE_MEMORY",
0349 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module Memory",
0350 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory."
0351 },
0352 {
0353 "Unit": "CPU-M-CF",
0354 "EventCode": "182",
0355 "EventName": "ICW_ON_DRAWER_MEMORY",
0356 "BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer Memory",
0357 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
0358 },
0359 {
0360 "Unit": "CPU-M-CF",
0361 "EventCode": "183",
0362 "EventName": "ICW_OFF_DRAWER_MEMORY",
0363 "BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer Memory",
0364 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory."
0365 },
0366 {
0367 "Unit": "CPU-M-CF",
0368 "EventCode": "224",
0369 "EventName": "BCD_DFP_EXECUTION_SLOTS",
0370 "BriefDescription": "Binary Coded Decimal to Decimal Floating Point conversions",
0371 "PublicDescription": "Count of floating point execution slots used for finished Binary Coded Decimal to Decimal Floating Point conversions. Instructions: CDZT, CXZT, CZDT, CZXT."
0372 },
0373 {
0374 "Unit": "CPU-M-CF",
0375 "EventCode": "225",
0376 "EventName": "VX_BCD_EXECUTION_SLOTS",
0377 "BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions",
0378 "PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG."
0379 },
0380 {
0381 "Unit": "CPU-M-CF",
0382 "EventCode": "226",
0383 "EventName": "DECIMAL_INSTRUCTIONS",
0384 "BriefDescription": "Decimal instruction dispatched",
0385 "PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP."
0386 },
0387 {
0388 "Unit": "CPU-M-CF",
0389 "EventCode": "232",
0390 "EventName": "LAST_HOST_TRANSLATIONS",
0391 "BriefDescription": "Last host translation done",
0392 "PublicDescription": "Last Host Translation done"
0393 },
0394 {
0395 "Unit": "CPU-M-CF",
0396 "EventCode": "244",
0397 "EventName": "TX_NC_TABORT",
0398 "BriefDescription": "Aborted transactions in unconstrained TX mode",
0399 "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
0400 },
0401 {
0402 "Unit": "CPU-M-CF",
0403 "EventCode": "245",
0404 "EventName": "TX_C_TABORT_NO_SPECIAL",
0405 "BriefDescription": "Aborted transactions in constrained TX mode",
0406 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
0407 },
0408 {
0409 "Unit": "CPU-M-CF",
0410 "EventCode": "246",
0411 "EventName": "TX_C_TABORT_SPECIAL",
0412 "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
0413 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
0414 },
0415 {
0416 "Unit": "CPU-M-CF",
0417 "EventCode": "248",
0418 "EventName": "DFLT_ACCESS",
0419 "BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
0420 "PublicDescription": "Cycles CPU spent obtaining access to Deflate unit"
0421 },
0422 {
0423 "Unit": "CPU-M-CF",
0424 "EventCode": "253",
0425 "EventName": "DFLT_CYCLES",
0426 "BriefDescription": "Cycles CPU is using Deflate unit",
0427 "PublicDescription": "Cycles CPU is using Deflate unit"
0428 },
0429 {
0430 "Unit": "CPU-M-CF",
0431 "EventCode": "256",
0432 "EventName": "SORTL",
0433 "BriefDescription": "Count SORTL instructions",
0434 "PublicDescription": "Increments by one for every SORT LISTS instruction executed."
0435 },
0436 {
0437 "Unit": "CPU-M-CF",
0438 "EventCode": "265",
0439 "EventName": "DFLT_CC",
0440 "BriefDescription": "Increments DEFLATE CONVERSION CALL",
0441 "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed."
0442 },
0443 {
0444 "Unit": "CPU-M-CF",
0445 "EventCode": "266",
0446 "EventName": "DFLT_CCFINISH",
0447 "BriefDescription": "Increments completed DEFLATE CONVERSION CALL",
0448 "PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL instruction executed that ended in Condition Codes 0, 1 or 2."
0449 },
0450 {
0451 "Unit": "CPU-M-CF",
0452 "EventCode": "267",
0453 "EventName": "NNPA_INVOCATIONS",
0454 "BriefDescription": "NNPA Total invocations",
0455 "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed."
0456 },
0457 {
0458 "Unit": "CPU-M-CF",
0459 "EventCode": "268",
0460 "EventName": "NNPA_COMPLETIONS",
0461 "BriefDescription": "NNPA Total completions",
0462 "PublicDescription": "Increments by one for every Neural Network Processing Assist instruction executed that ended in Condition Codes 0, 1 or 2."
0463 },
0464 {
0465 "Unit": "CPU-M-CF",
0466 "EventCode": "269",
0467 "EventName": "NNPA_WAIT_LOCK",
0468 "BriefDescription": "Cycles spent obtaining NNPA lock",
0469 "PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI."
0470 },
0471 {
0472 "Unit": "CPU-M-CF",
0473 "EventCode": "270",
0474 "EventName": "NNPA_HOLD_LOCK",
0475 "BriefDescription": "Cycles spent holding NNPA lock",
0476 "PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI."
0477 },
0478 {
0479 "Unit": "CPU-M-CF",
0480 "EventCode": "448",
0481 "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
0482 "BriefDescription": "Cycle count with one thread active",
0483 "PublicDescription": "Cycle count with one thread active"
0484 },
0485 {
0486 "Unit": "CPU-M-CF",
0487 "EventCode": "449",
0488 "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
0489 "BriefDescription": "Cycle count with two threads active",
0490 "PublicDescription": "Cycle count with two threads active"
0491 }
0492 ]
