0001 [
0002 {
0003 "Unit": "CPU-M-CF",
0004 "EventCode": "128",
0005 "EventName": "L1D_RO_EXCL_WRITES",
0006 "BriefDescription": "L1D Read-only Exclusive Writes",
0007 "PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
0008 },
0009 {
0010 "Unit": "CPU-M-CF",
0011 "EventCode": "129",
0012 "EventName": "DTLB1_WRITES",
0013 "BriefDescription": "DTLB1 Writes",
0014 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
0015 },
0016 {
0017 "Unit": "CPU-M-CF",
0018 "EventCode": "130",
0019 "EventName": "DTLB1_MISSES",
0020 "BriefDescription": "DTLB1 Misses",
0021 "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle a DTLB1 miss is in progress."
0022 },
0023 {
0024 "Unit": "CPU-M-CF",
0025 "EventCode": "131",
0026 "EventName": "DTLB1_HPAGE_WRITES",
0027 "BriefDescription": "DTLB1 One-Megabyte Page Writes",
0028 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a one-megabyte page."
0029 },
0030 {
0031 "Unit": "CPU-M-CF",
0032 "EventCode": "132",
0033 "EventName": "DTLB1_GPAGE_WRITES",
0034 "BriefDescription": "DTLB1 Two-Gigabyte Page Writes",
0035 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer for a two-gigabyte page."
0036 },
0037 {
0038 "Unit": "CPU-M-CF",
0039 "EventCode": "133",
0040 "EventName": "L1D_L2D_SOURCED_WRITES",
0041 "BriefDescription": "L1D L2D Sourced Writes",
0042 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the Level-2 Data cache."
0043 },
0044 {
0045 "Unit": "CPU-M-CF",
0046 "EventCode": "134",
0047 "EventName": "ITLB1_WRITES",
0048 "BriefDescription": "ITLB1 Writes",
0049 "PublicDescription": "A translation entry has been written to the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
0050 },
0051 {
0052 "Unit": "CPU-M-CF",
0053 "EventCode": "135",
0054 "EventName": "ITLB1_MISSES",
0055 "BriefDescription": "ITLB1 Misses",
0056 "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress."
0057 },
0058 {
0059 "Unit": "CPU-M-CF",
0060 "EventCode": "136",
0061 "EventName": "L1I_L2I_SOURCED_WRITES",
0062 "BriefDescription": "L1I L2I Sourced Writes",
0063 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the Level-2 Instruction cache."
0064 },
0065 {
0066 "Unit": "CPU-M-CF",
0067 "EventCode": "137",
0068 "EventName": "TLB2_PTE_WRITES",
0069 "BriefDescription": "TLB2 PTE Writes",
0070 "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
0071 },
0072 {
0073 "Unit": "CPU-M-CF",
0074 "EventCode": "138",
0075 "EventName": "TLB2_CRSTE_HPAGE_WRITES",
0076 "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
0077 "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays for a one-megabyte large page translation."
0078 },
0079 {
0080 "Unit": "CPU-M-CF",
0081 "EventCode": "139",
0082 "EventName": "TLB2_CRSTE_WRITES",
0083 "BriefDescription": "TLB2 CRSTE Writes",
0084 "PublicDescription": "A translation entry has been written to the Level-2 TLB Combined Region Segment Table Entry arrays."
0085 },
0086 {
0087 "Unit": "CPU-M-CF",
0088 "EventCode": "140",
0089 "EventName": "TX_C_TEND",
0090 "BriefDescription": "Completed TEND instructions in constrained TX mode",
0091 "PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
0092 },
0093 {
0094 "Unit": "CPU-M-CF",
0095 "EventCode": "141",
0096 "EventName": "TX_NC_TEND",
0097 "BriefDescription": "Completed TEND instructions in non-constrained TX mode",
0098 "PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
0099 },
0100 {
0101 "Unit": "CPU-M-CF",
0102 "EventCode": "143",
0103 "EventName": "L1C_TLB1_MISSES",
0104 "BriefDescription": "L1C TLB1 Misses",
0105 "PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-1 TLB miss is in progress."
0106 },
0107 {
0108 "Unit": "CPU-M-CF",
0109 "EventCode": "144",
0110 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES",
0111 "BriefDescription": "L1D On-Chip L3 Sourced Writes",
0112 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention."
0113 },
0114 {
0115 "Unit": "CPU-M-CF",
0116 "EventCode": "145",
0117 "EventName": "L1D_ONCHIP_L3_SOURCED_WRITES_IV",
0118 "BriefDescription": "L1D On-Chip L3 Sourced Writes with Intervention",
0119 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-3 cache with intervention."
0120 },
0121 {
0122 "Unit": "CPU-M-CF",
0123 "EventCode": "146",
0124 "EventName": "L1D_ONNODE_L4_SOURCED_WRITES",
0125 "BriefDescription": "L1D On-Node L4 Sourced Writes",
0126 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-4 cache."
0127 },
0128 {
0129 "Unit": "CPU-M-CF",
0130 "EventCode": "147",
0131 "EventName": "L1D_ONNODE_L3_SOURCED_WRITES_IV",
0132 "BriefDescription": "L1D On-Node L3 Sourced Writes with Intervention",
0133 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention."
0134 },
0135 {
0136 "Unit": "CPU-M-CF",
0137 "EventCode": "148",
0138 "EventName": "L1D_ONNODE_L3_SOURCED_WRITES",
0139 "BriefDescription": "L1D On-Node L3 Sourced Writes",
0140 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention."
0141 },
0142 {
0143 "Unit": "CPU-M-CF",
0144 "EventCode": "149",
0145 "EventName": "L1D_ONDRAWER_L4_SOURCED_WRITES",
0146 "BriefDescription": "L1D On-Drawer L4 Sourced Writes",
0147 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache."
0148 },
0149 {
0150 "Unit": "CPU-M-CF",
0151 "EventCode": "150",
0152 "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES_IV",
0153 "BriefDescription": "L1D On-Drawer L3 Sourced Writes with Intervention",
0154 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention."
0155 },
0156 {
0157 "Unit": "CPU-M-CF",
0158 "EventCode": "151",
0159 "EventName": "L1D_ONDRAWER_L3_SOURCED_WRITES",
0160 "BriefDescription": "L1D On-Drawer L3 Sourced Writes",
0161 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention."
0162 },
0163 {
0164 "Unit": "CPU-M-CF",
0165 "EventCode": "152",
0166 "EventName": "L1D_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
0167 "BriefDescription": "L1D Off-Drawer Same-Column L4 Sourced Writes",
0168 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache."
0169 },
0170 {
0171 "Unit": "CPU-M-CF",
0172 "EventCode": "153",
0173 "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
0174 "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes with Intervention",
0175 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention."
0176 },
0177 {
0178 "Unit": "CPU-M-CF",
0179 "EventCode": "154",
0180 "EventName": "L1D_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
0181 "BriefDescription": "L1D Off-Drawer Same-Column L3 Sourced Writes",
0182 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention."
0183 },
0184 {
0185 "Unit": "CPU-M-CF",
0186 "EventCode": "155",
0187 "EventName": "L1D_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
0188 "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
0189 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache."
0190 },
0191 {
0192 "Unit": "CPU-M-CF",
0193 "EventCode": "156",
0194 "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
0195 "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes with Intervention",
0196 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention."
0197 },
0198 {
0199 "Unit": "CPU-M-CF",
0200 "EventCode": "157",
0201 "EventName": "L1D_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
0202 "BriefDescription": "L1D Off-Drawer Far-Column L3 Sourced Writes",
0203 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention."
0204 },
0205 {
0206 "Unit": "CPU-M-CF",
0207 "EventCode": "158",
0208 "EventName": "L1D_ONNODE_MEM_SOURCED_WRITES",
0209 "BriefDescription": "L1D On-Node Memory Sourced Writes",
0210 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Node memory."
0211 },
0212 {
0213 "Unit": "CPU-M-CF",
0214 "EventCode": "159",
0215 "EventName": "L1D_ONDRAWER_MEM_SOURCED_WRITES",
0216 "BriefDescription": "L1D On-Drawer Memory Sourced Writes",
0217 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Drawer memory."
0218 },
0219 {
0220 "Unit": "CPU-M-CF",
0221 "EventCode": "160",
0222 "EventName": "L1D_OFFDRAWER_MEM_SOURCED_WRITES",
0223 "BriefDescription": "L1D Off-Drawer Memory Sourced Writes",
0224 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from Off-Drawer memory."
0225 },
0226 {
0227 "Unit": "CPU-M-CF",
0228 "EventCode": "161",
0229 "EventName": "L1D_ONCHIP_MEM_SOURCED_WRITES",
0230 "BriefDescription": "L1D On-Chip Memory Sourced Writes",
0231 "PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from On-Chip memory."
0232 },
0233 {
0234 "Unit": "CPU-M-CF",
0235 "EventCode": "162",
0236 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES",
0237 "BriefDescription": "L1I On-Chip L3 Sourced Writes",
0238 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-3 cache without intervention."
0239 },
0240 {
0241 "Unit": "CPU-M-CF",
0242 "EventCode": "163",
0243 "EventName": "L1I_ONCHIP_L3_SOURCED_WRITES_IV",
0244 "BriefDescription": "L1I On-Chip L3 Sourced Writes with Intervention",
0245 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On Chip Level-3 cache with intervention."
0246 },
0247 {
0248 "Unit": "CPU-M-CF",
0249 "EventCode": "164",
0250 "EventName": "L1I_ONNODE_L4_SOURCED_WRITES",
0251 "BriefDescription": "L1I On-Chip L4 Sourced Writes",
0252 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-4 cache."
0253 },
0254 {
0255 "Unit": "CPU-M-CF",
0256 "EventCode": "165",
0257 "EventName": "L1I_ONNODE_L3_SOURCED_WRITES_IV",
0258 "BriefDescription": "L1I On-Node L3 Sourced Writes with Intervention",
0259 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache with intervention."
0260 },
0261 {
0262 "Unit": "CPU-M-CF",
0263 "EventCode": "166",
0264 "EventName": "L1I_ONNODE_L3_SOURCED_WRITES",
0265 "BriefDescription": "L1I On-Node L3 Sourced Writes",
0266 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Node Level-3 cache without intervention."
0267 },
0268 {
0269 "Unit": "CPU-M-CF",
0270 "EventCode": "167",
0271 "EventName": "L1I_ONDRAWER_L4_SOURCED_WRITES",
0272 "BriefDescription": "L1I On-Drawer L4 Sourced Writes",
0273 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-4 cache."
0274 },
0275 {
0276 "Unit": "CPU-M-CF",
0277 "EventCode": "168",
0278 "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES_IV",
0279 "BriefDescription": "L1I On-Drawer L3 Sourced Writes with Intervention",
0280 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache with intervention."
0281 },
0282 {
0283 "Unit": "CPU-M-CF",
0284 "EventCode": "169",
0285 "EventName": "L1I_ONDRAWER_L3_SOURCED_WRITES",
0286 "BriefDescription": "L1I On-Drawer L3 Sourced Writes",
0287 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-3 cache without intervention."
0288 },
0289 {
0290 "Unit": "CPU-M-CF",
0291 "EventCode": "170",
0292 "EventName": "L1I_OFFDRAWER_SCOL_L4_SOURCED_WRITES",
0293 "BriefDescription": "L1I Off-Drawer Same-Column L4 Sourced Writes",
0294 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-4 cache."
0295 },
0296 {
0297 "Unit": "CPU-M-CF",
0298 "EventCode": "171",
0299 "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES_IV",
0300 "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes with Intervention",
0301 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache with intervention."
0302 },
0303 {
0304 "Unit": "CPU-M-CF",
0305 "EventCode": "172",
0306 "EventName": "L1I_OFFDRAWER_SCOL_L3_SOURCED_WRITES",
0307 "BriefDescription": "L1I Off-Drawer Same-Column L3 Sourced Writes",
0308 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Same-Column Level-3 cache without intervention."
0309 },
0310 {
0311 "Unit": "CPU-M-CF",
0312 "EventCode": "173",
0313 "EventName": "L1I_OFFDRAWER_FCOL_L4_SOURCED_WRITES",
0314 "BriefDescription": "L1I Off-Drawer Far-Column L4 Sourced Writes",
0315 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-4 cache."
0316 },
0317 {
0318 "Unit": "CPU-M-CF",
0319 "EventCode": "174",
0320 "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES_IV",
0321 "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes with Intervention",
0322 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache with intervention."
0323 },
0324 {
0325 "Unit": "CPU-M-CF",
0326 "EventCode": "175",
0327 "EventName": "L1I_OFFDRAWER_FCOL_L3_SOURCED_WRITES",
0328 "BriefDescription": "L1I Off-Drawer Far-Column L3 Sourced Writes",
0329 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Far-Column Level-3 cache without intervention."
0330 },
0331 {
0332 "Unit": "CPU-M-CF",
0333 "EventCode": "176",
0334 "EventName": "L1I_ONNODE_MEM_SOURCED_WRITES",
0335 "BriefDescription": "L1I On-Node Memory Sourced Writes",
0336 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Node memory."
0337 },
0338 {
0339 "Unit": "CPU-M-CF",
0340 "EventCode": "177",
0341 "EventName": "L1I_ONDRAWER_MEM_SOURCED_WRITES",
0342 "BriefDescription": "L1I On-Drawer Memory Sourced Writes",
0343 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
0344 },
0345 {
0346 "Unit": "CPU-M-CF",
0347 "EventCode": "178",
0348 "EventName": "L1I_OFFDRAWER_MEM_SOURCED_WRITES",
0349 "BriefDescription": "L1I Off-Drawer Memory Sourced Writes",
0350 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
0351 },
0352 {
0353 "Unit": "CPU-M-CF",
0354 "EventCode": "179",
0355 "EventName": "L1I_ONCHIP_MEM_SOURCED_WRITES",
0356 "BriefDescription": "L1I On-Chip Memory Sourced Writes",
0357 "PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
0358 },
0359 {
0360 "Unit": "CPU-M-CF",
0361 "EventCode": "218",
0362 "EventName": "TX_NC_TABORT",
0363 "BriefDescription": "Aborted transactions in non-constrained TX mode",
0364 "PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
0365 },
0366 {
0367 "Unit": "CPU-M-CF",
0368 "EventCode": "219",
0369 "EventName": "TX_C_TABORT_NO_SPECIAL",
0370 "BriefDescription": "Aborted transactions in constrained TX mode not using special completion logic",
0371 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
0372 },
0373 {
0374 "Unit": "CPU-M-CF",
0375 "EventCode": "220",
0376 "EventName": "TX_C_TABORT_SPECIAL",
0377 "BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
0378 "PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
0379 },
0380 {
0381 "Unit": "CPU-M-CF",
0382 "EventCode": "448",
0383 "EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
0384 "BriefDescription": "Cycle count with one thread active",
0385 "PublicDescription": "Cycle count with one thread active"
0386 },
0387 {
0388 "Unit": "CPU-M-CF",
0389 "EventCode": "449",
0390 "EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
0391 "BriefDescription": "Cycle count with two threads active",
0392 "PublicDescription": "Cycle count with two threads active"
0393 }
0394 ]
