0001 [
0002 {
0003 "Unit": "CPU-M-CF",
0004 "EventCode": "128",
0005 "EventName": "L1I_L2_SOURCED_WRITES",
0006 "BriefDescription": "L1I L2 Sourced Writes",
0007 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the returned cache line was sourced from the Level-2 (L1.5) cache."
0008 },
0009 {
0010 "Unit": "CPU-M-CF",
0011 "EventCode": "129",
0012 "EventName": "L1D_L2_SOURCED_WRITES",
0013 "BriefDescription": "L1D L2 Sourced Writes",
0014 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from the Level-2 (L1.5) cache."
0015 },
0016 {
0017 "Unit": "CPU-M-CF",
0018 "EventCode": "130",
0019 "EventName": "L1I_L3_LOCAL_WRITES",
0020 "BriefDescription": "L1I L3 Local Writes",
0021 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from the Level-3 cache that is on the same book as the Instruction cache (Local L2 cache)."
0022 },
0023 {
0024 "Unit": "CPU-M-CF",
0025 "EventCode": "131",
0026 "EventName": "L1D_L3_LOCAL_WRITES",
0027 "BriefDescription": "L1D L3 Local Writes",
0028 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was source from the Level-3 cache that is on the same book as the Data cache (Local L2 cache)."
0029 },
0030 {
0031 "Unit": "CPU-M-CF",
0032 "EventCode": "132",
0033 "EventName": "L1I_L3_REMOTE_WRITES",
0034 "BriefDescription": "L1I L3 Remote Writes",
0035 "PublicDescription": "A directory write to the Level-1 Instruction Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Instruction cache (Remote L2 cache)."
0036 },
0037 {
0038 "Unit": "CPU-M-CF",
0039 "EventCode": "133",
0040 "EventName": "L1D_L3_REMOTE_WRITES",
0041 "BriefDescription": "L1D L3 Remote Writes",
0042 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from a Level-3 cache that is not on the same book as the Data cache (Remote L2 cache)."
0043 },
0044 {
0045 "Unit": "CPU-M-CF",
0046 "EventCode": "134",
0047 "EventName": "L1D_LMEM_SOURCED_WRITES",
0048 "BriefDescription": "L1D Local Memory Sourced Writes",
0049 "PublicDescription": "A directory write to the Level-1 Data Cache directory where the installed cache line was sourced from memory that is attached to the same book as the Data cache (Local Memory)."
0050 },
0051 {
0052 "Unit": "CPU-M-CF",
0053 "EventCode": "135",
0054 "EventName": "L1I_LMEM_SOURCED_WRITES",
0055 "BriefDescription": "L1I Local Memory Sourced Writes",
0056 "PublicDescription": "A directory write to the Level-1 Instruction Cache where the installed cache line was sourced from memory that is attached to the s ame book as the Instruction cache (Local Memory)."
0057 },
0058 {
0059 "Unit": "CPU-M-CF",
0060 "EventCode": "136",
0061 "EventName": "L1D_RO_EXCL_WRITES",
0062 "BriefDescription": "L1D Read-only Exclusive Writes",
0063 "PublicDescription": "A directory write to the Level-1 Data Cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
0064 },
0065 {
0066 "Unit": "CPU-M-CF",
0067 "EventCode": "137",
0068 "EventName": "L1I_CACHELINE_INVALIDATES",
0069 "BriefDescription": "L1I Cacheline Invalidates",
0070 "PublicDescription": "A cache line in the Level-1 Instruction Cache has been invalidated by a store on the same CPU as the Level-1 Instruction Cache."
0071 },
0072 {
0073 "Unit": "CPU-M-CF",
0074 "EventCode": "138",
0075 "EventName": "ITLB1_WRITES",
0076 "BriefDescription": "ITLB1 Writes",
0077 "PublicDescription": "A translation entry has been written into the Level-1 Instruction Translation Lookaside Buffer (ITLB1)."
0078 },
0079 {
0080 "Unit": "CPU-M-CF",
0081 "EventCode": "139",
0082 "EventName": "DTLB1_WRITES",
0083 "BriefDescription": "DTLB1 Writes",
0084 "PublicDescription": "A translation entry has been written to the Level-1 Data Translation Lookaside Buffer (DTLB1)."
0085 },
0086 {
0087 "Unit": "CPU-M-CF",
0088 "EventCode": "140",
0089 "EventName": "TLB2_PTE_WRITES",
0090 "BriefDescription": "TLB2 PTE Writes",
0091 "PublicDescription": "A translation entry has been written to the Level-2 TLB Page Table Entry arrays."
0092 },
0093 {
0094 "Unit": "CPU-M-CF",
0095 "EventCode": "141",
0096 "EventName": "TLB2_CRSTE_WRITES",
0097 "BriefDescription": "TLB2 CRSTE Writes",
0098 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays."
0099 },
0100 {
0101 "Unit": "CPU-M-CF",
0102 "EventCode": "142",
0103 "EventName": "TLB2_CRSTE_HPAGE_WRITES",
0104 "BriefDescription": "TLB2 CRSTE One-Megabyte Page Writes",
0105 "PublicDescription": "A translation entry has been written to the Level-2 TLB Common Region Segment Table Entry arrays for a one-megabyte large page translation."
0106 },
0107 {
0108 "Unit": "CPU-M-CF",
0109 "EventCode": "145",
0110 "EventName": "ITLB1_MISSES",
0111 "BriefDescription": "ITLB1 Misses",
0112 "PublicDescription": "Level-1 Instruction TLB miss in progress. Incremented by one for every cycle an ITLB1 miss is in progress."
0113 },
0114 {
0115 "Unit": "CPU-M-CF",
0116 "EventCode": "146",
0117 "EventName": "DTLB1_MISSES",
0118 "BriefDescription": "DTLB1 Misses",
0119 "PublicDescription": "Level-1 Data TLB miss in progress. Incremented by one for every cycle an DTLB1 miss is in progress."
0120 },
0121 {
0122 "Unit": "CPU-M-CF",
0123 "EventCode": "147",
0124 "EventName": "L2C_STORES_SENT",
0125 "BriefDescription": "L2C Stores Sent",
0126 "PublicDescription": "Incremented by one for every store sent to Level-2 (L1.5) cache."
0127 }
0128 ]
