0001 [
0002 {
0003 "EventCode": "0x20036",
0004 "EventName": "PM_BR_2PATH",
0005 "BriefDescription": "Branches that are not strongly biased"
0006 },
0007 {
0008 "EventCode": "0x40056",
0009 "EventName": "PM_MEM_LOC_THRESH_LSU_HIGH",
0010 "BriefDescription": "Local memory above threshold for LSU medium"
0011 },
0012 {
0013 "EventCode": "0x40118",
0014 "EventName": "PM_MRK_DCACHE_RELOAD_INTV",
0015 "BriefDescription": "Combined Intervention event"
0016 },
0017 {
0018 "EventCode": "0x4F148",
0019 "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
0020 "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
0021 },
0022 {
0023 "EventCode": "0x301E8",
0024 "EventName": "PM_THRESH_EXC_64",
0025 "BriefDescription": "Threshold counter exceeded a value of 64"
0026 },
0027 {
0028 "EventCode": "0x4E04E",
0029 "EventName": "PM_DPTEG_FROM_L3MISS",
0030 "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
0031 },
0032 {
0033 "EventCode": "0x40050",
0034 "EventName": "PM_SYS_PUMP_MPRED_RTY",
0035 "BriefDescription": "Final Pump Scope (system) ended up larger than Initial Pump Scope (Chip/Group) for all data types excluding data prefetch (demand load,inst prefetch,inst fetch,xlate)"
0036 },
0037 {
0038 "EventCode": "0x1F14E",
0039 "EventName": "PM_MRK_DPTEG_FROM_L2MISS",
0040 "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request.. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
0041 },
0042 {
0043 "EventCode": "0x4D018",
0044 "EventName": "PM_CMPLU_STALL_BRU",
0045 "BriefDescription": "Completion stall due to a Branch Unit"
0046 },
0047 {
0048 "EventCode": "0x45052",
0049 "EventName": "PM_4FLOP_CMPL",
0050 "BriefDescription": "4 FLOP instruction completed"
0051 },
0052 {
0053 "EventCode": "0x3D142",
0054 "EventName": "PM_MRK_DATA_FROM_LMEM",
0055 "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load"
0056 },
0057 {
0058 "EventCode": "0x4C01E",
0059 "EventName": "PM_CMPLU_STALL_CRYPTO",
0060 "BriefDescription": "Finish stall because the NTF instruction was routed to the crypto execution pipe and was waiting to finish"
0061 },
0062 {
0063 "EventCode": "0x3000C",
0064 "EventName": "PM_FREQ_DOWN",
0065 "BriefDescription": "Power Management: Below Threshold B"
0066 },
0067 {
0068 "EventCode": "0x4D128",
0069 "EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
0070 "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load"
0071 },
0072 {
0073 "EventCode": "0x4D054",
0074 "EventName": "PM_8FLOP_CMPL",
0075 "BriefDescription": "8 FLOP instruction completed"
0076 },
0077 {
0078 "EventCode": "0x10026",
0079 "EventName": "PM_TABLEWALK_CYC",
0080 "BriefDescription": "Cycles when an instruction tablewalk is active"
0081 },
0082 {
0083 "EventCode": "0x2C012",
0084 "EventName": "PM_CMPLU_STALL_DCACHE_MISS",
0085 "BriefDescription": "Finish stall because the NTF instruction was a load that missed the L1 and was waiting for the data to return from the nest"
0086 },
0087 {
0088 "EventCode": "0x2E04C",
0089 "EventName": "PM_DPTEG_FROM_MEMORY",
0090 "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
0091 },
0092 {
0093 "EventCode": "0x3F142",
0094 "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
0095 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
0096 },
0097 {
0098 "EventCode": "0x4F142",
0099 "EventName": "PM_MRK_DPTEG_FROM_L3",
0100 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
0101 },
0102 {
0103 "EventCode": "0x10060",
0104 "EventName": "PM_TM_TRANS_RUN_CYC",
0105 "BriefDescription": "run cycles in transactional state"
0106 },
0107 {
0108 "EventCode": "0x1E04C",
0109 "EventName": "PM_DPTEG_FROM_LL4",
0110 "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a data side request. When using Radix Page Translation, this count excludes PDE reloads. Only PTE reloads are included"
0111 },
0112 {
0113 "EventCode": "0x45050",
0114 "EventName": "PM_1FLOP_CMPL",
0115 "BriefDescription": "one flop (fadd, fmul, fsub, fcmp, fsel, fabs, fnabs, fres, fsqrte, fneg) operation completed"
0116 }
0117 ]
