0001 [
0002 {
0003 "EventCode": "0x1415A",
0004 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
0005 "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load"
0006 },
0007 {
0008 "EventCode": "0x10058",
0009 "EventName": "PM_MEM_LOC_THRESH_IFU",
0010 "BriefDescription": "Local Memory above threshold for IFU speculation control"
0011 },
0012 {
0013 "EventCode": "0x2D028",
0014 "EventName": "PM_RADIX_PWC_L2_PDE_FROM_L2",
0015 "BriefDescription": "A Page Directory Entry was reloaded to a level 2 page walk cache from the core's L2 data cache"
0016 },
0017 {
0018 "EventCode": "0x30012",
0019 "EventName": "PM_FLUSH_COMPLETION",
0020 "BriefDescription": "The instruction that was next to complete did not complete because it suffered a flush"
0021 },
0022 {
0023 "EventCode": "0x2D154",
0024 "EventName": "PM_MRK_DERAT_MISS_64K",
0025 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K"
0026 },
0027 {
0028 "EventCode": "0x4016E",
0029 "EventName": "PM_THRESH_NOT_MET",
0030 "BriefDescription": "Threshold counter did not meet threshold"
0031 }
0032 ]
