0001 [
0002 {
0003 "EventCode": "0x100f2",
0004 "EventName": "PM_1PLUS_PPC_CMPL",
0005 "BriefDescription": "1 or more ppc insts finished",
0006 "PublicDescription": "1 or more ppc insts finished (completed)"
0007 },
0008 {
0009 "EventCode": "0x400f2",
0010 "EventName": "PM_1PLUS_PPC_DISP",
0011 "BriefDescription": "Cycles at least one Instr Dispatched",
0012 "PublicDescription": "Cycles at least one Instr Dispatched. Could be a group with only microcode. Issue HW016521"
0013 },
0014 {
0015 "EventCode": "0x100fa",
0016 "EventName": "PM_ANY_THRD_RUN_CYC",
0017 "BriefDescription": "One of threads in run_cycles",
0018 "PublicDescription": "Any thread in run_cycles (was one thread in run_cycles)"
0019 },
0020 {
0021 "EventCode": "0x4000a",
0022 "EventName": "PM_CMPLU_STALL",
0023 "BriefDescription": "Completion stall",
0024 "PublicDescription": ""
0025 },
0026 {
0027 "EventCode": "0x4d018",
0028 "EventName": "PM_CMPLU_STALL_BRU",
0029 "BriefDescription": "Completion stall due to a Branch Unit",
0030 "PublicDescription": ""
0031 },
0032 {
0033 "EventCode": "0x2c012",
0034 "EventName": "PM_CMPLU_STALL_DCACHE_MISS",
0035 "BriefDescription": "Completion stall by Dcache miss",
0036 "PublicDescription": ""
0037 },
0038 {
0039 "EventCode": "0x2c018",
0040 "EventName": "PM_CMPLU_STALL_DMISS_L21_L31",
0041 "BriefDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)",
0042 "PublicDescription": ""
0043 },
0044 {
0045 "EventCode": "0x2c016",
0046 "EventName": "PM_CMPLU_STALL_DMISS_L2L3",
0047 "BriefDescription": "Completion stall by Dcache miss which resolved in L2/L3",
0048 "PublicDescription": ""
0049 },
0050 {
0051 "EventCode": "0x4c016",
0052 "EventName": "PM_CMPLU_STALL_DMISS_L2L3_CONFLICT",
0053 "BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a conflict",
0054 "PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict"
0055 },
0056 {
0057 "EventCode": "0x4c01a",
0058 "EventName": "PM_CMPLU_STALL_DMISS_L3MISS",
0059 "BriefDescription": "Completion stall due to cache miss resolving missed the L3",
0060 "PublicDescription": ""
0061 },
0062 {
0063 "EventCode": "0x4c018",
0064 "EventName": "PM_CMPLU_STALL_DMISS_LMEM",
0065 "BriefDescription": "Completion stall due to cache miss that resolves in local memory",
0066 "PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory"
0067 },
0068 {
0069 "EventCode": "0x2c01c",
0070 "EventName": "PM_CMPLU_STALL_DMISS_REMOTE",
0071 "BriefDescription": "Completion stall by Dcache miss which resolved from remote chip (cache or memory)",
0072 "PublicDescription": "Completion stall by Dcache miss which resolved on chip ( excluding local L2/L3)"
0073 },
0074 {
0075 "EventCode": "0x4c012",
0076 "EventName": "PM_CMPLU_STALL_ERAT_MISS",
0077 "BriefDescription": "Completion stall due to LSU reject ERAT miss",
0078 "PublicDescription": ""
0079 },
0080 {
0081 "EventCode": "0x4d016",
0082 "EventName": "PM_CMPLU_STALL_FXLONG",
0083 "BriefDescription": "Completion stall due to a long latency fixed point instruction",
0084 "PublicDescription": ""
0085 },
0086 {
0087 "EventCode": "0x2d016",
0088 "EventName": "PM_CMPLU_STALL_FXU",
0089 "BriefDescription": "Completion stall due to FXU",
0090 "PublicDescription": ""
0091 },
0092 {
0093 "EventCode": "0x30036",
0094 "EventName": "PM_CMPLU_STALL_HWSYNC",
0095 "BriefDescription": "completion stall due to hwsync",
0096 "PublicDescription": ""
0097 },
0098 {
0099 "EventCode": "0x4d014",
0100 "EventName": "PM_CMPLU_STALL_LOAD_FINISH",
0101 "BriefDescription": "Completion stall due to a Load finish",
0102 "PublicDescription": ""
0103 },
0104 {
0105 "EventCode": "0x2c010",
0106 "EventName": "PM_CMPLU_STALL_LSU",
0107 "BriefDescription": "Completion stall by LSU instruction",
0108 "PublicDescription": ""
0109 },
0110 {
0111 "EventCode": "0x10036",
0112 "EventName": "PM_CMPLU_STALL_LWSYNC",
0113 "BriefDescription": "completion stall due to isync/lwsync",
0114 "PublicDescription": ""
0115 },
0116 {
0117 "EventCode": "0x30006",
0118 "EventName": "PM_CMPLU_STALL_OTHER_CMPL",
0119 "BriefDescription": "Instructions core completed while this tread was stalled",
0120 "PublicDescription": "Instructions core completed while this thread was stalled"
0121 },
0122 {
0123 "EventCode": "0x4c01c",
0124 "EventName": "PM_CMPLU_STALL_ST_FWD",
0125 "BriefDescription": "Completion stall due to store forward",
0126 "PublicDescription": ""
0127 },
0128 {
0129 "EventCode": "0x1001c",
0130 "EventName": "PM_CMPLU_STALL_THRD",
0131 "BriefDescription": "Completion Stalled due to thread conflict. Group ready to complete but it was another thread's turn",
0132 "PublicDescription": "Completion stall due to thread conflict"
0133 },
0134 {
0135 "EventCode": "0x1e",
0136 "EventName": "PM_CYC",
0137 "BriefDescription": "Cycles",
0138 "PublicDescription": ""
0139 },
0140 {
0141 "EventCode": "0x10006",
0142 "EventName": "PM_DISP_HELD",
0143 "BriefDescription": "Dispatch Held",
0144 "PublicDescription": ""
0145 },
0146 {
0147 "EventCode": "0x4003c",
0148 "EventName": "PM_DISP_HELD_SYNC_HOLD",
0149 "BriefDescription": "Dispatch held due to SYNC hold",
0150 "PublicDescription": ""
0151 },
0152 {
0153 "EventCode": "0x200f8",
0154 "EventName": "PM_EXT_INT",
0155 "BriefDescription": "external interrupt",
0156 "PublicDescription": ""
0157 },
0158 {
0159 "EventCode": "0x400f8",
0160 "EventName": "PM_FLUSH",
0161 "BriefDescription": "Flush (any type)",
0162 "PublicDescription": ""
0163 },
0164 {
0165 "EventCode": "0x30012",
0166 "EventName": "PM_FLUSH_COMPLETION",
0167 "BriefDescription": "Completion Flush",
0168 "PublicDescription": ""
0169 },
0170 {
0171 "EventCode": "0x3000c",
0172 "EventName": "PM_FREQ_DOWN",
0173 "BriefDescription": "Power Management: Below Threshold B",
0174 "PublicDescription": "Frequency is being slewed down due to Power Management"
0175 },
0176 {
0177 "EventCode": "0x4000c",
0178 "EventName": "PM_FREQ_UP",
0179 "BriefDescription": "Power Management: Above Threshold A",
0180 "PublicDescription": "Frequency is being slewed up due to Power Management"
0181 },
0182 {
0183 "EventCode": "0x2000a",
0184 "EventName": "PM_HV_CYC",
0185 "BriefDescription": "Cycles in which msr_hv is high. Note that this event does not take msr_pr into consideration",
0186 "PublicDescription": "cycles in hypervisor mode"
0187 },
0188 {
0189 "EventCode": "0x3405e",
0190 "EventName": "PM_IFETCH_THROTTLE",
0191 "BriefDescription": "Cycles in which Instruction fetch throttle was active",
0192 "PublicDescription": "Cycles instruction fecth was throttled in IFU"
0193 },
0194 {
0195 "EventCode": "0x10014",
0196 "EventName": "PM_IOPS_CMPL",
0197 "BriefDescription": "Internal Operations completed",
0198 "PublicDescription": "IOPS Completed"
0199 },
0200 {
0201 "EventCode": "0x3c058",
0202 "EventName": "PM_LARX_FIN",
0203 "BriefDescription": "Larx finished",
0204 "PublicDescription": ""
0205 },
0206 {
0207 "EventCode": "0x1002e",
0208 "EventName": "PM_LD_CMPL",
0209 "BriefDescription": "count of Loads completed",
0210 "PublicDescription": ""
0211 },
0212 {
0213 "EventCode": "0x10062",
0214 "EventName": "PM_LD_L3MISS_PEND_CYC",
0215 "BriefDescription": "Cycles L3 miss was pending for this thread",
0216 "PublicDescription": ""
0217 },
0218 {
0219 "EventCode": "0x30066",
0220 "EventName": "PM_LSU_FIN",
0221 "BriefDescription": "LSU Finished an instruction (up to 2 per cycle)",
0222 "PublicDescription": ""
0223 },
0224 {
0225 "EventCode": "0x2003e",
0226 "EventName": "PM_LSU_LMQ_SRQ_EMPTY_CYC",
0227 "BriefDescription": "LSU empty (lmq and srq empty)",
0228 "PublicDescription": ""
0229 },
0230 {
0231 "EventCode": "0x2e05c",
0232 "EventName": "PM_LSU_REJECT_ERAT_MISS",
0233 "BriefDescription": "LSU Reject due to ERAT (up to 4 per cycles)",
0234 "PublicDescription": ""
0235 },
0236 {
0237 "EventCode": "0x4e05c",
0238 "EventName": "PM_LSU_REJECT_LHS",
0239 "BriefDescription": "LSU Reject due to LHS (up to 4 per cycle)",
0240 "PublicDescription": ""
0241 },
0242 {
0243 "EventCode": "0x1e05c",
0244 "EventName": "PM_LSU_REJECT_LMQ_FULL",
0245 "BriefDescription": "LSU reject due to LMQ full ( 4 per cycle)",
0246 "PublicDescription": ""
0247 },
0248 {
0249 "EventCode": "0x1001a",
0250 "EventName": "PM_LSU_SRQ_FULL_CYC",
0251 "BriefDescription": "Storage Queue is full and is blocking dispatch",
0252 "PublicDescription": "SRQ is Full"
0253 },
0254 {
0255 "EventCode": "0x40014",
0256 "EventName": "PM_PROBE_NOP_DISP",
0257 "BriefDescription": "ProbeNops dispatched",
0258 "PublicDescription": ""
0259 },
0260 {
0261 "EventCode": "0x600f4",
0262 "EventName": "PM_RUN_CYC",
0263 "BriefDescription": "Run_cycles",
0264 "PublicDescription": ""
0265 },
0266 {
0267 "EventCode": "0x3006c",
0268 "EventName": "PM_RUN_CYC_SMT2_MODE",
0269 "BriefDescription": "Cycles run latch is set and core is in SMT2 mode",
0270 "PublicDescription": ""
0271 },
0272 {
0273 "EventCode": "0x2006c",
0274 "EventName": "PM_RUN_CYC_SMT4_MODE",
0275 "BriefDescription": "cycles this threads run latch is set and the core is in SMT4 mode",
0276 "PublicDescription": "Cycles run latch is set and core is in SMT4 mode"
0277 },
0278 {
0279 "EventCode": "0x1006c",
0280 "EventName": "PM_RUN_CYC_ST_MODE",
0281 "BriefDescription": "Cycles run latch is set and core is in ST mode",
0282 "PublicDescription": ""
0283 },
0284 {
0285 "EventCode": "0x500fa",
0286 "EventName": "PM_RUN_INST_CMPL",
0287 "BriefDescription": "Run_Instructions",
0288 "PublicDescription": ""
0289 },
0290 {
0291 "EventCode": "0x1e058",
0292 "EventName": "PM_STCX_FAIL",
0293 "BriefDescription": "stcx failed",
0294 "PublicDescription": ""
0295 },
0296 {
0297 "EventCode": "0x20016",
0298 "EventName": "PM_ST_CMPL",
0299 "BriefDescription": "Store completion count",
0300 "PublicDescription": ""
0301 },
0302 {
0303 "EventCode": "0x200f0",
0304 "EventName": "PM_ST_FIN",
0305 "BriefDescription": "Store Instructions Finished",
0306 "PublicDescription": "Store Instructions Finished (store sent to nest)"
0307 },
0308 {
0309 "EventCode": "0x20018",
0310 "EventName": "PM_ST_FWD",
0311 "BriefDescription": "Store forwards that finished",
0312 "PublicDescription": ""
0313 },
0314 {
0315 "EventCode": "0x10026",
0316 "EventName": "PM_TABLEWALK_CYC",
0317 "BriefDescription": "Cycles when a tablewalk (I or D) is active",
0318 "PublicDescription": "Tablewalk Active"
0319 },
0320 {
0321 "EventCode": "0x300f8",
0322 "EventName": "PM_TB_BIT_TRANS",
0323 "BriefDescription": "timebase event",
0324 "PublicDescription": ""
0325 },
0326 {
0327 "EventCode": "0x2000c",
0328 "EventName": "PM_THRD_ALL_RUN_CYC",
0329 "BriefDescription": "All Threads in Run_cycles (was both threads in run_cycles)",
0330 "PublicDescription": ""
0331 },
0332 {
0333 "EventCode": "0x30058",
0334 "EventName": "PM_TLBIE_FIN",
0335 "BriefDescription": "tlbie finished",
0336 "PublicDescription": ""
0337 },
0338 {
0339 "EventCode": "0x10060",
0340 "EventName": "PM_TM_TRANS_RUN_CYC",
0341 "BriefDescription": "run cycles in transactional state",
0342 "PublicDescription": ""
0343 },
0344 {
0345 "EventCode": "0x2e012",
0346 "EventName": "PM_TM_TX_PASS_RUN_CYC",
0347 "BriefDescription": "cycles spent in successful transactions",
0348 "PublicDescription": "run cycles spent in successful transactions"
0349 }
0350 ]
