0001 [
0002 {
0003 "EventCode": "0x3515e",
0004 "EventName": "PM_MRK_BACK_BR_CMPL",
0005 "BriefDescription": "Marked branch instruction completed with a target address less than current instruction address",
0006 "PublicDescription": ""
0007 },
0008 {
0009 "EventCode": "0x2013a",
0010 "EventName": "PM_MRK_BRU_FIN",
0011 "BriefDescription": "bru marked instr finish",
0012 "PublicDescription": ""
0013 },
0014 {
0015 "EventCode": "0x1016e",
0016 "EventName": "PM_MRK_BR_CMPL",
0017 "BriefDescription": "Branch Instruction completed",
0018 "PublicDescription": ""
0019 },
0020 {
0021 "EventCode": "0x301e4",
0022 "EventName": "PM_MRK_BR_MPRED_CMPL",
0023 "BriefDescription": "Marked Branch Mispredicted",
0024 "PublicDescription": ""
0025 },
0026 {
0027 "EventCode": "0x101e2",
0028 "EventName": "PM_MRK_BR_TAKEN_CMPL",
0029 "BriefDescription": "Marked Branch Taken completed",
0030 "PublicDescription": ""
0031 },
0032 {
0033 "EventCode": "0x4d148",
0034 "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD",
0035 "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
0036 "PublicDescription": ""
0037 },
0038 {
0039 "EventCode": "0x2d128",
0040 "EventName": "PM_MRK_DATA_FROM_DL2L3_MOD_CYC",
0041 "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
0042 "PublicDescription": ""
0043 },
0044 {
0045 "EventCode": "0x3d148",
0046 "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR",
0047 "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
0048 "PublicDescription": ""
0049 },
0050 {
0051 "EventCode": "0x2c128",
0052 "EventName": "PM_MRK_DATA_FROM_DL2L3_SHR_CYC",
0053 "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load",
0054 "PublicDescription": ""
0055 },
0056 {
0057 "EventCode": "0x3d14c",
0058 "EventName": "PM_MRK_DATA_FROM_DL4",
0059 "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load",
0060 "PublicDescription": ""
0061 },
0062 {
0063 "EventCode": "0x2c12c",
0064 "EventName": "PM_MRK_DATA_FROM_DL4_CYC",
0065 "BriefDescription": "Duration in cycles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load",
0066 "PublicDescription": ""
0067 },
0068 {
0069 "EventCode": "0x4d14c",
0070 "EventName": "PM_MRK_DATA_FROM_DMEM",
0071 "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load",
0072 "PublicDescription": ""
0073 },
0074 {
0075 "EventCode": "0x2d12c",
0076 "EventName": "PM_MRK_DATA_FROM_DMEM_CYC",
0077 "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group (Distant) due to a marked load",
0078 "PublicDescription": ""
0079 },
0080 {
0081 "EventCode": "0x1d142",
0082 "EventName": "PM_MRK_DATA_FROM_L2",
0083 "BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked load",
0084 "PublicDescription": ""
0085 },
0086 {
0087 "EventCode": "0x1d14e",
0088 "EventName": "PM_MRK_DATA_FROM_L2MISS",
0089 "BriefDescription": "Data cache reload L2 miss",
0090 "PublicDescription": ""
0091 },
0092 {
0093 "EventCode": "0x4c12e",
0094 "EventName": "PM_MRK_DATA_FROM_L2MISS_CYC",
0095 "BriefDescription": "Duration in cycles to reload from a location other than the local core's L2 due to a marked load",
0096 "PublicDescription": ""
0097 },
0098 {
0099 "EventCode": "0x4c122",
0100 "EventName": "PM_MRK_DATA_FROM_L2_CYC",
0101 "BriefDescription": "Duration in cycles to reload from local core's L2 due to a marked load",
0102 "PublicDescription": ""
0103 },
0104 {
0105 "EventCode": "0x3d140",
0106 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST",
0107 "BriefDescription": "The processor's data cache was reloaded from local core's L2 with load hit store conflict due to a marked load",
0108 "PublicDescription": ""
0109 },
0110 {
0111 "EventCode": "0x2c120",
0112 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_LDHITST_CYC",
0113 "BriefDescription": "Duration in cycles to reload from local core's L2 with load hit store conflict due to a marked load",
0114 "PublicDescription": ""
0115 },
0116 {
0117 "EventCode": "0x4d140",
0118 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER",
0119 "BriefDescription": "The processor's data cache was reloaded from local core's L2 with dispatch conflict due to a marked load",
0120 "PublicDescription": ""
0121 },
0122 {
0123 "EventCode": "0x2d120",
0124 "EventName": "PM_MRK_DATA_FROM_L2_DISP_CONFLICT_OTHER_CYC",
0125 "BriefDescription": "Duration in cycles to reload from local core's L2 with dispatch conflict due to a marked load",
0126 "PublicDescription": ""
0127 },
0128 {
0129 "EventCode": "0x2d140",
0130 "EventName": "PM_MRK_DATA_FROM_L2_MEPF",
0131 "BriefDescription": "The processor's data cache was reloaded from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
0132 "PublicDescription": ""
0133 },
0134 {
0135 "EventCode": "0x4d120",
0136 "EventName": "PM_MRK_DATA_FROM_L2_MEPF_CYC",
0137 "BriefDescription": "Duration in cycles to reload from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked load",
0138 "PublicDescription": ""
0139 },
0140 {
0141 "EventCode": "0x1d140",
0142 "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT",
0143 "BriefDescription": "The processor's data cache was reloaded from local core's L2 without conflict due to a marked load",
0144 "PublicDescription": ""
0145 },
0146 {
0147 "EventCode": "0x4c120",
0148 "EventName": "PM_MRK_DATA_FROM_L2_NO_CONFLICT_CYC",
0149 "BriefDescription": "Duration in cycles to reload from local core's L2 without conflict due to a marked load",
0150 "PublicDescription": ""
0151 },
0152 {
0153 "EventCode": "0x4d142",
0154 "EventName": "PM_MRK_DATA_FROM_L3",
0155 "BriefDescription": "The processor's data cache was reloaded from local core's L3 due to a marked load",
0156 "PublicDescription": ""
0157 },
0158 {
0159 "EventCode": "0x201e4",
0160 "EventName": "PM_MRK_DATA_FROM_L3MISS",
0161 "BriefDescription": "The processor's data cache was reloaded from a location other than the local core's L3 due to a marked load",
0162 "PublicDescription": ""
0163 },
0164 {
0165 "EventCode": "0x2d12e",
0166 "EventName": "PM_MRK_DATA_FROM_L3MISS_CYC",
0167 "BriefDescription": "Duration in cycles to reload from a location other than the local core's L3 due to a marked load",
0168 "PublicDescription": ""
0169 },
0170 {
0171 "EventCode": "0x2d122",
0172 "EventName": "PM_MRK_DATA_FROM_L3_CYC",
0173 "BriefDescription": "Duration in cycles to reload from local core's L3 due to a marked load",
0174 "PublicDescription": ""
0175 },
0176 {
0177 "EventCode": "0x3d142",
0178 "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT",
0179 "BriefDescription": "The processor's data cache was reloaded from local core's L3 with dispatch conflict due to a marked load",
0180 "PublicDescription": ""
0181 },
0182 {
0183 "EventCode": "0x2c122",
0184 "EventName": "PM_MRK_DATA_FROM_L3_DISP_CONFLICT_CYC",
0185 "BriefDescription": "Duration in cycles to reload from local core's L3 with dispatch conflict due to a marked load",
0186 "PublicDescription": ""
0187 },
0188 {
0189 "EventCode": "0x2d142",
0190 "EventName": "PM_MRK_DATA_FROM_L3_MEPF",
0191 "BriefDescription": "The processor's data cache was reloaded from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
0192 "PublicDescription": ""
0193 },
0194 {
0195 "EventCode": "0x4d122",
0196 "EventName": "PM_MRK_DATA_FROM_L3_MEPF_CYC",
0197 "BriefDescription": "Duration in cycles to reload from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked load",
0198 "PublicDescription": ""
0199 },
0200 {
0201 "EventCode": "0x1d144",
0202 "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT",
0203 "BriefDescription": "The processor's data cache was reloaded from local core's L3 without conflict due to a marked load",
0204 "PublicDescription": ""
0205 },
0206 {
0207 "EventCode": "0x4c124",
0208 "EventName": "PM_MRK_DATA_FROM_L3_NO_CONFLICT_CYC",
0209 "BriefDescription": "Duration in cycles to reload from local core's L3 without conflict due to a marked load",
0210 "PublicDescription": ""
0211 },
0212 {
0213 "EventCode": "0x1d14c",
0214 "EventName": "PM_MRK_DATA_FROM_LL4",
0215 "BriefDescription": "The processor's data cache was reloaded from the local chip's L4 cache due to a marked load",
0216 "PublicDescription": ""
0217 },
0218 {
0219 "EventCode": "0x4c12c",
0220 "EventName": "PM_MRK_DATA_FROM_LL4_CYC",
0221 "BriefDescription": "Duration in cycles to reload from the local chip's L4 cache due to a marked load",
0222 "PublicDescription": ""
0223 },
0224 {
0225 "EventCode": "0x2d148",
0226 "EventName": "PM_MRK_DATA_FROM_LMEM",
0227 "BriefDescription": "The processor's data cache was reloaded from the local chip's Memory due to a marked load",
0228 "PublicDescription": ""
0229 },
0230 {
0231 "EventCode": "0x4d128",
0232 "EventName": "PM_MRK_DATA_FROM_LMEM_CYC",
0233 "BriefDescription": "Duration in cycles to reload from the local chip's Memory due to a marked load",
0234 "PublicDescription": ""
0235 },
0236 {
0237 "EventCode": "0x2d14c",
0238 "EventName": "PM_MRK_DATA_FROM_MEMORY",
0239 "BriefDescription": "The processor's data cache was reloaded from a memory location including L4 from local remote or distant due to a marked load",
0240 "PublicDescription": ""
0241 },
0242 {
0243 "EventCode": "0x4d12c",
0244 "EventName": "PM_MRK_DATA_FROM_MEMORY_CYC",
0245 "BriefDescription": "Duration in cycles to reload from a memory location including L4 from local remote or distant due to a marked load",
0246 "PublicDescription": ""
0247 },
0248 {
0249 "EventCode": "0x4d14a",
0250 "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE",
0251 "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
0252 "PublicDescription": ""
0253 },
0254 {
0255 "EventCode": "0x2d12a",
0256 "EventName": "PM_MRK_DATA_FROM_OFF_CHIP_CACHE_CYC",
0257 "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked load",
0258 "PublicDescription": ""
0259 },
0260 {
0261 "EventCode": "0x1d148",
0262 "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE",
0263 "BriefDescription": "The processor's data cache was reloaded either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
0264 "PublicDescription": ""
0265 },
0266 {
0267 "EventCode": "0x4c128",
0268 "EventName": "PM_MRK_DATA_FROM_ON_CHIP_CACHE_CYC",
0269 "BriefDescription": "Duration in cycles to reload either shared or modified data from another core's L2/L3 on the same chip due to a marked load",
0270 "PublicDescription": ""
0271 },
0272 {
0273 "EventCode": "0x2d146",
0274 "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD",
0275 "BriefDescription": "The processor's data cache was reloaded with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
0276 "PublicDescription": ""
0277 },
0278 {
0279 "EventCode": "0x4d126",
0280 "EventName": "PM_MRK_DATA_FROM_RL2L3_MOD_CYC",
0281 "BriefDescription": "Duration in cycles to reload with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
0282 "PublicDescription": ""
0283 },
0284 {
0285 "EventCode": "0x1d14a",
0286 "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR",
0287 "BriefDescription": "The processor's data cache was reloaded with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
0288 "PublicDescription": ""
0289 },
0290 {
0291 "EventCode": "0x4c12a",
0292 "EventName": "PM_MRK_DATA_FROM_RL2L3_SHR_CYC",
0293 "BriefDescription": "Duration in cycles to reload with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked load",
0294 "PublicDescription": ""
0295 },
0296 {
0297 "EventCode": "0x2d14a",
0298 "EventName": "PM_MRK_DATA_FROM_RL4",
0299 "BriefDescription": "The processor's data cache was reloaded from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
0300 "PublicDescription": ""
0301 },
0302 {
0303 "EventCode": "0x4d12a",
0304 "EventName": "PM_MRK_DATA_FROM_RL4_CYC",
0305 "BriefDescription": "Duration in cycles to reload from another chip's L4 on the same Node or Group ( Remote) due to a marked load",
0306 "PublicDescription": ""
0307 },
0308 {
0309 "EventCode": "0x3d14a",
0310 "EventName": "PM_MRK_DATA_FROM_RMEM",
0311 "BriefDescription": "The processor's data cache was reloaded from another chip's memory on the same Node or Group ( Remote) due to a marked load",
0312 "PublicDescription": ""
0313 },
0314 {
0315 "EventCode": "0x2c12a",
0316 "EventName": "PM_MRK_DATA_FROM_RMEM_CYC",
0317 "BriefDescription": "Duration in cycles to reload from another chip's memory on the same Node or Group ( Remote) due to a marked load",
0318 "PublicDescription": ""
0319 },
0320 {
0321 "EventCode": "0x40118",
0322 "EventName": "PM_MRK_DCACHE_RELOAD_INTV",
0323 "BriefDescription": "Combined Intervention event",
0324 "PublicDescription": ""
0325 },
0326 {
0327 "EventCode": "0x301e6",
0328 "EventName": "PM_MRK_DERAT_MISS",
0329 "BriefDescription": "Erat Miss (TLB Access) All page sizes",
0330 "PublicDescription": ""
0331 },
0332 {
0333 "EventCode": "0x4d154",
0334 "EventName": "PM_MRK_DERAT_MISS_16G",
0335 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16G",
0336 "PublicDescription": ""
0337 },
0338 {
0339 "EventCode": "0x3d154",
0340 "EventName": "PM_MRK_DERAT_MISS_16M",
0341 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 16M",
0342 "PublicDescription": ""
0343 },
0344 {
0345 "EventCode": "0x1d156",
0346 "EventName": "PM_MRK_DERAT_MISS_4K",
0347 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 4K",
0348 "PublicDescription": ""
0349 },
0350 {
0351 "EventCode": "0x2d154",
0352 "EventName": "PM_MRK_DERAT_MISS_64K",
0353 "BriefDescription": "Marked Data ERAT Miss (Data TLB Access) page size 64K",
0354 "PublicDescription": ""
0355 },
0356 {
0357 "EventCode": "0x20132",
0358 "EventName": "PM_MRK_DFU_FIN",
0359 "BriefDescription": "Decimal Unit marked Instruction Finish",
0360 "PublicDescription": ""
0361 },
0362 {
0363 "EventCode": "0x4f148",
0364 "EventName": "PM_MRK_DPTEG_FROM_DL2L3_MOD",
0365 "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
0366 "PublicDescription": ""
0367 },
0368 {
0369 "EventCode": "0x3f148",
0370 "EventName": "PM_MRK_DPTEG_FROM_DL2L3_SHR",
0371 "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked data side request",
0372 "PublicDescription": ""
0373 },
0374 {
0375 "EventCode": "0x3f14c",
0376 "EventName": "PM_MRK_DPTEG_FROM_DL4",
0377 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on a different Node or Group (Distant) due to a marked data side request",
0378 "PublicDescription": ""
0379 },
0380 {
0381 "EventCode": "0x4f14c",
0382 "EventName": "PM_MRK_DPTEG_FROM_DMEM",
0383 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group (Distant) due to a marked data side request",
0384 "PublicDescription": ""
0385 },
0386 {
0387 "EventCode": "0x1f142",
0388 "EventName": "PM_MRK_DPTEG_FROM_L2",
0389 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a marked data side request",
0390 "PublicDescription": ""
0391 },
0392 {
0393 "EventCode": "0x1f14e",
0394 "EventName": "PM_MRK_DPTEG_FROM_L2MISS",
0395 "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L2 due to a marked data side request",
0396 "PublicDescription": ""
0397 },
0398 {
0399 "EventCode": "0x2f140",
0400 "EventName": "PM_MRK_DPTEG_FROM_L2_MEPF",
0401 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a marked data side request",
0402 "PublicDescription": ""
0403 },
0404 {
0405 "EventCode": "0x1f140",
0406 "EventName": "PM_MRK_DPTEG_FROM_L2_NO_CONFLICT",
0407 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 without conflict due to a marked data side request",
0408 "PublicDescription": ""
0409 },
0410 {
0411 "EventCode": "0x4f142",
0412 "EventName": "PM_MRK_DPTEG_FROM_L3",
0413 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a marked data side request",
0414 "PublicDescription": ""
0415 },
0416 {
0417 "EventCode": "0x4f14e",
0418 "EventName": "PM_MRK_DPTEG_FROM_L3MISS",
0419 "BriefDescription": "A Page Table Entry was loaded into the TLB from a location other than the local core's L3 due to a marked data side request",
0420 "PublicDescription": ""
0421 },
0422 {
0423 "EventCode": "0x3f142",
0424 "EventName": "PM_MRK_DPTEG_FROM_L3_DISP_CONFLICT",
0425 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a marked data side request",
0426 "PublicDescription": ""
0427 },
0428 {
0429 "EventCode": "0x2f142",
0430 "EventName": "PM_MRK_DPTEG_FROM_L3_MEPF",
0431 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a marked data side request",
0432 "PublicDescription": ""
0433 },
0434 {
0435 "EventCode": "0x1f144",
0436 "EventName": "PM_MRK_DPTEG_FROM_L3_NO_CONFLICT",
0437 "BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 without conflict due to a marked data side request",
0438 "PublicDescription": ""
0439 },
0440 {
0441 "EventCode": "0x1f14c",
0442 "EventName": "PM_MRK_DPTEG_FROM_LL4",
0443 "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data side request",
0444 "PublicDescription": ""
0445 },
0446 {
0447 "EventCode": "0x2f148",
0448 "EventName": "PM_MRK_DPTEG_FROM_LMEM",
0449 "BriefDescription": "A Page Table Entry was loaded into the TLB from the local chip's Memory due to a marked data side request",
0450 "PublicDescription": ""
0451 },
0452 {
0453 "EventCode": "0x2f14c",
0454 "EventName": "PM_MRK_DPTEG_FROM_MEMORY",
0455 "BriefDescription": "A Page Table Entry was loaded into the TLB from a memory location including L4 from local remote or distant due to a marked data side request",
0456 "PublicDescription": ""
0457 },
0458 {
0459 "EventCode": "0x4f14a",
0460 "EventName": "PM_MRK_DPTEG_FROM_OFF_CHIP_CACHE",
0461 "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on a different chip (remote or distant) due to a marked data side request",
0462 "PublicDescription": ""
0463 },
0464 {
0465 "EventCode": "0x1f148",
0466 "EventName": "PM_MRK_DPTEG_FROM_ON_CHIP_CACHE",
0467 "BriefDescription": "A Page Table Entry was loaded into the TLB either shared or modified data from another core's L2/L3 on the same chip due to a marked data side request",
0468 "PublicDescription": ""
0469 },
0470 {
0471 "EventCode": "0x2f146",
0472 "EventName": "PM_MRK_DPTEG_FROM_RL2L3_MOD",
0473 "BriefDescription": "A Page Table Entry was loaded into the TLB with Modified (M) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
0474 "PublicDescription": ""
0475 },
0476 {
0477 "EventCode": "0x1f14a",
0478 "EventName": "PM_MRK_DPTEG_FROM_RL2L3_SHR",
0479 "BriefDescription": "A Page Table Entry was loaded into the TLB with Shared (S) data from another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a marked data side request",
0480 "PublicDescription": ""
0481 },
0482 {
0483 "EventCode": "0x2f14a",
0484 "EventName": "PM_MRK_DPTEG_FROM_RL4",
0485 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's L4 on the same Node or Group ( Remote) due to a marked data side request",
0486 "PublicDescription": ""
0487 },
0488 {
0489 "EventCode": "0x3f14a",
0490 "EventName": "PM_MRK_DPTEG_FROM_RMEM",
0491 "BriefDescription": "A Page Table Entry was loaded into the TLB from another chip's memory on the same Node or Group ( Remote) due to a marked data side request",
0492 "PublicDescription": ""
0493 },
0494 {
0495 "EventCode": "0x401e4",
0496 "EventName": "PM_MRK_DTLB_MISS",
0497 "BriefDescription": "Marked dtlb miss",
0498 "PublicDescription": ""
0499 },
0500 {
0501 "EventCode": "0x1d158",
0502 "EventName": "PM_MRK_DTLB_MISS_16G",
0503 "BriefDescription": "Marked Data TLB Miss page size 16G",
0504 "PublicDescription": ""
0505 },
0506 {
0507 "EventCode": "0x4d156",
0508 "EventName": "PM_MRK_DTLB_MISS_16M",
0509 "BriefDescription": "Marked Data TLB Miss page size 16M",
0510 "PublicDescription": ""
0511 },
0512 {
0513 "EventCode": "0x2d156",
0514 "EventName": "PM_MRK_DTLB_MISS_4K",
0515 "BriefDescription": "Marked Data TLB Miss page size 4k",
0516 "PublicDescription": ""
0517 },
0518 {
0519 "EventCode": "0x3d156",
0520 "EventName": "PM_MRK_DTLB_MISS_64K",
0521 "BriefDescription": "Marked Data TLB Miss page size 64K",
0522 "PublicDescription": ""
0523 },
0524 {
0525 "EventCode": "0x40154",
0526 "EventName": "PM_MRK_FAB_RSP_BKILL",
0527 "BriefDescription": "Marked store had to do a bkill",
0528 "PublicDescription": ""
0529 },
0530 {
0531 "EventCode": "0x2f150",
0532 "EventName": "PM_MRK_FAB_RSP_BKILL_CYC",
0533 "BriefDescription": "cycles L2 RC took for a bkill",
0534 "PublicDescription": ""
0535 },
0536 {
0537 "EventCode": "0x3015e",
0538 "EventName": "PM_MRK_FAB_RSP_CLAIM_RTY",
0539 "BriefDescription": "Sampled store did a rwitm and got a rty",
0540 "PublicDescription": ""
0541 },
0542 {
0543 "EventCode": "0x30154",
0544 "EventName": "PM_MRK_FAB_RSP_DCLAIM",
0545 "BriefDescription": "Marked store had to do a dclaim",
0546 "PublicDescription": ""
0547 },
0548 {
0549 "EventCode": "0x2f152",
0550 "EventName": "PM_MRK_FAB_RSP_DCLAIM_CYC",
0551 "BriefDescription": "cycles L2 RC took for a dclaim",
0552 "PublicDescription": ""
0553 },
0554 {
0555 "EventCode": "0x4015e",
0556 "EventName": "PM_MRK_FAB_RSP_RD_RTY",
0557 "BriefDescription": "Sampled L2 reads retry count",
0558 "PublicDescription": ""
0559 },
0560 {
0561 "EventCode": "0x1015e",
0562 "EventName": "PM_MRK_FAB_RSP_RD_T_INTV",
0563 "BriefDescription": "Sampled Read got a T intervention",
0564 "PublicDescription": ""
0565 },
0566 {
0567 "EventCode": "0x4f150",
0568 "EventName": "PM_MRK_FAB_RSP_RWITM_CYC",
0569 "BriefDescription": "cycles L2 RC took for a rwitm",
0570 "PublicDescription": ""
0571 },
0572 {
0573 "EventCode": "0x2015e",
0574 "EventName": "PM_MRK_FAB_RSP_RWITM_RTY",
0575 "BriefDescription": "Sampled store did a rwitm and got a rty",
0576 "PublicDescription": ""
0577 },
0578 {
0579 "EventCode": "0x20134",
0580 "EventName": "PM_MRK_FXU_FIN",
0581 "BriefDescription": "fxu marked instr finish",
0582 "PublicDescription": ""
0583 },
0584 {
0585 "EventCode": "0x401e0",
0586 "EventName": "PM_MRK_INST_CMPL",
0587 "BriefDescription": "marked instruction completed",
0588 "PublicDescription": ""
0589 },
0590 {
0591 "EventCode": "0x20130",
0592 "EventName": "PM_MRK_INST_DECODED",
0593 "BriefDescription": "marked instruction decoded",
0594 "PublicDescription": "marked instruction decoded. Name from ISU?"
0595 },
0596 {
0597 "EventCode": "0x101e0",
0598 "EventName": "PM_MRK_INST_DISP",
0599 "BriefDescription": "The thread has dispatched a randomly sampled marked instruction",
0600 "PublicDescription": "Marked Instruction dispatched"
0601 },
0602 {
0603 "EventCode": "0x30130",
0604 "EventName": "PM_MRK_INST_FIN",
0605 "BriefDescription": "marked instruction finished",
0606 "PublicDescription": "marked instr finish any unit"
0607 },
0608 {
0609 "EventCode": "0x401e6",
0610 "EventName": "PM_MRK_INST_FROM_L3MISS",
0611 "BriefDescription": "Marked instruction was reloaded from a location beyond the local chiplet",
0612 "PublicDescription": "n/a"
0613 },
0614 {
0615 "EventCode": "0x10132",
0616 "EventName": "PM_MRK_INST_ISSUED",
0617 "BriefDescription": "Marked instruction issued",
0618 "PublicDescription": ""
0619 },
0620 {
0621 "EventCode": "0x40134",
0622 "EventName": "PM_MRK_INST_TIMEO",
0623 "BriefDescription": "marked Instruction finish timeout (instruction lost)",
0624 "PublicDescription": ""
0625 },
0626 {
0627 "EventCode": "0x101e4",
0628 "EventName": "PM_MRK_L1_ICACHE_MISS",
0629 "BriefDescription": "sampled Instruction suffered an icache Miss",
0630 "PublicDescription": "Marked L1 Icache Miss"
0631 },
0632 {
0633 "EventCode": "0x101ea",
0634 "EventName": "PM_MRK_L1_RELOAD_VALID",
0635 "BriefDescription": "Marked demand reload",
0636 "PublicDescription": ""
0637 },
0638 {
0639 "EventCode": "0x20114",
0640 "EventName": "PM_MRK_L2_RC_DISP",
0641 "BriefDescription": "Marked Instruction RC dispatched in L2",
0642 "PublicDescription": ""
0643 },
0644 {
0645 "EventCode": "0x3012a",
0646 "EventName": "PM_MRK_L2_RC_DONE",
0647 "BriefDescription": "Marked RC done",
0648 "PublicDescription": ""
0649 },
0650 {
0651 "EventCode": "0x40116",
0652 "EventName": "PM_MRK_LARX_FIN",
0653 "BriefDescription": "Larx finished",
0654 "PublicDescription": ""
0655 },
0656 {
0657 "EventCode": "0x1013e",
0658 "EventName": "PM_MRK_LD_MISS_EXPOSED_CYC",
0659 "BriefDescription": "Marked Load exposed Miss cycles",
0660 "PublicDescription": "Marked Load exposed Miss (use edge detect to count #)"
0661 },
0662 {
0663 "EventCode": "0x201e2",
0664 "EventName": "PM_MRK_LD_MISS_L1",
0665 "BriefDescription": "Marked DL1 Demand Miss counted at exec time",
0666 "PublicDescription": ""
0667 },
0668 {
0669 "EventCode": "0x4013e",
0670 "EventName": "PM_MRK_LD_MISS_L1_CYC",
0671 "BriefDescription": "Marked ld latency",
0672 "PublicDescription": ""
0673 },
0674 {
0675 "EventCode": "0x40132",
0676 "EventName": "PM_MRK_LSU_FIN",
0677 "BriefDescription": "lsu marked instr finish",
0678 "PublicDescription": ""
0679 },
0680 {
0681 "EventCode": "0x20112",
0682 "EventName": "PM_MRK_NTF_FIN",
0683 "BriefDescription": "Marked next to finish instruction finished",
0684 "PublicDescription": ""
0685 },
0686 {
0687 "EventCode": "0x1d15e",
0688 "EventName": "PM_MRK_RUN_CYC",
0689 "BriefDescription": "Marked run cycles",
0690 "PublicDescription": ""
0691 },
0692 {
0693 "EventCode": "0x3013e",
0694 "EventName": "PM_MRK_STALL_CMPLU_CYC",
0695 "BriefDescription": "Marked Group completion Stall",
0696 "PublicDescription": "Marked Group Completion Stall cycles (use edge detect to count #)"
0697 },
0698 {
0699 "EventCode": "0x3e158",
0700 "EventName": "PM_MRK_STCX_FAIL",
0701 "BriefDescription": "marked stcx failed",
0702 "PublicDescription": ""
0703 },
0704 {
0705 "EventCode": "0x10134",
0706 "EventName": "PM_MRK_ST_CMPL",
0707 "BriefDescription": "marked store completed and sent to nest",
0708 "PublicDescription": "Marked store completed"
0709 },
0710 {
0711 "EventCode": "0x30134",
0712 "EventName": "PM_MRK_ST_CMPL_INT",
0713 "BriefDescription": "marked store finished with intervention",
0714 "PublicDescription": "marked store complete (data home) with intervention"
0715 },
0716 {
0717 "EventCode": "0x3f150",
0718 "EventName": "PM_MRK_ST_DRAIN_TO_L2DISP_CYC",
0719 "BriefDescription": "cycles to drain st from core to L2",
0720 "PublicDescription": ""
0721 },
0722 {
0723 "EventCode": "0x3012c",
0724 "EventName": "PM_MRK_ST_FWD",
0725 "BriefDescription": "Marked st forwards",
0726 "PublicDescription": ""
0727 },
0728 {
0729 "EventCode": "0x1f150",
0730 "EventName": "PM_MRK_ST_L2DISP_TO_CMPL_CYC",
0731 "BriefDescription": "cycles from L2 rc disp to l2 rc completion",
0732 "PublicDescription": ""
0733 },
0734 {
0735 "EventCode": "0x20138",
0736 "EventName": "PM_MRK_ST_NEST",
0737 "BriefDescription": "Marked store sent to nest",
0738 "PublicDescription": ""
0739 },
0740 {
0741 "EventCode": "0x30132",
0742 "EventName": "PM_MRK_VSU_FIN",
0743 "BriefDescription": "VSU marked instr finish",
0744 "PublicDescription": "vsu (fpu) marked instr finish"
0745 },
0746 {
0747 "EventCode": "0x3d15e",
0748 "EventName": "PM_MULT_MRK",
0749 "BriefDescription": "mult marked instr",
0750 "PublicDescription": ""
0751 },
0752 {
0753 "EventCode": "0x15152",
0754 "EventName": "PM_SYNC_MRK_BR_LINK",
0755 "BriefDescription": "Marked Branch and link branch that can cause a synchronous interrupt",
0756 "PublicDescription": ""
0757 },
0758 {
0759 "EventCode": "0x1515c",
0760 "EventName": "PM_SYNC_MRK_BR_MPRED",
0761 "BriefDescription": "Marked Branch mispredict that can cause a synchronous interrupt",
0762 "PublicDescription": ""
0763 },
0764 {
0765 "EventCode": "0x15156",
0766 "EventName": "PM_SYNC_MRK_FX_DIVIDE",
0767 "BriefDescription": "Marked fixed point divide that can cause a synchronous interrupt",
0768 "PublicDescription": ""
0769 },
0770 {
0771 "EventCode": "0x15158",
0772 "EventName": "PM_SYNC_MRK_L2HIT",
0773 "BriefDescription": "Marked L2 Hits that can throw a synchronous interrupt",
0774 "PublicDescription": ""
0775 },
0776 {
0777 "EventCode": "0x1515a",
0778 "EventName": "PM_SYNC_MRK_L2MISS",
0779 "BriefDescription": "Marked L2 Miss that can throw a synchronous interrupt",
0780 "PublicDescription": ""
0781 },
0782 {
0783 "EventCode": "0x15154",
0784 "EventName": "PM_SYNC_MRK_L3MISS",
0785 "BriefDescription": "Marked L3 misses that can throw a synchronous interrupt",
0786 "PublicDescription": ""
0787 },
0788 {
0789 "EventCode": "0x15150",
0790 "EventName": "PM_SYNC_MRK_PROBE_NOP",
0791 "BriefDescription": "Marked probeNops which can cause synchronous interrupts",
0792 "PublicDescription": ""
0793 }
0794 ]
