Back to home page

OSCL-LXR

 
 

    


0001 [
0002   {
0003     "EventCode": "0x1003C",
0004     "EventName": "PM_EXEC_STALL_DMISS_L2L3",
0005     "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from either the local L2 or local L3."
0006   },
0007   {
0008     "EventCode": "0x1E054",
0009     "EventName": "PM_EXEC_STALL_DMISS_L21_L31",
0010     "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from another core's L2 or L3 on the same chip."
0011   },
0012   {
0013     "EventCode": "0x34054",
0014     "EventName": "PM_EXEC_STALL_DMISS_L2L3_NOCONFLICT",
0015     "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, without a dispatch conflict."
0016   },
0017   {
0018     "EventCode": "0x34056",
0019     "EventName": "PM_EXEC_STALL_LOAD_FINISH",
0020     "BriefDescription": "Cycles in which the oldest instruction in the pipeline was finishing a load after its data was reloaded from a data source beyond the local L1; cycles in which the LSU was processing an L1-hit; cycles in which the NTF instruction merged with another load in the LMQ; cycles in which the NTF instruction is waiting for a data reload for a load miss, but the data comes back with a non-NTF instruction."
0021   },
0022   {
0023     "EventCode": "0x3006C",
0024     "EventName": "PM_RUN_CYC_SMT2_MODE",
0025     "BriefDescription": "Cycles when this thread's run latch is set and the core is in SMT2 mode."
0026   },
0027   {
0028     "EventCode": "0x300F4",
0029     "EventName": "PM_RUN_INST_CMPL_CONC",
0030     "BriefDescription": "PowerPC instructions completed by this thread when all threads in the core had the run-latch set."
0031   },
0032   {
0033     "EventCode": "0x4C016",
0034     "EventName": "PM_EXEC_STALL_DMISS_L2L3_CONFLICT",
0035     "BriefDescription": "Cycles in which the oldest instruction in the pipeline was waiting for a load miss to resolve from the local L2 or local L3, with a dispatch conflict."
0036   },
0037   {
0038     "EventCode": "0x4D014",
0039     "EventName": "PM_EXEC_STALL_LOAD",
0040     "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a load instruction executing in the Load Store Unit."
0041   },
0042   {
0043     "EventCode": "0x4D016",
0044     "EventName": "PM_EXEC_STALL_PTESYNC",
0045     "BriefDescription": "Cycles in which the oldest instruction in the pipeline was a PTESYNC instruction executing in the Load Store Unit."
0046   },
0047   {
0048     "EventCode": "0x401EA",
0049     "EventName": "PM_THRESH_EXC_128",
0050     "BriefDescription": "Threshold counter exceeded a value of 128."
0051   },
0052   {
0053     "EventCode": "0x400F6",
0054     "EventName": "PM_BR_MPRED_CMPL",
0055     "BriefDescription": "A mispredicted branch completed. Includes direction and target."
0056   }
0057 ]