0001 [
0002 {
0003 "ArchStdEvent": "SIMD_INST_RETIRED"
0004 },
0005 {
0006 "ArchStdEvent": "SVE_INST_RETIRED"
0007 },
0008 {
0009 "ArchStdEvent": "UOP_SPEC"
0010 },
0011 {
0012 "ArchStdEvent": "SVE_MATH_SPEC"
0013 },
0014 {
0015 "ArchStdEvent": "FP_SPEC"
0016 },
0017 {
0018 "ArchStdEvent": "FP_FMA_SPEC"
0019 },
0020 {
0021 "ArchStdEvent": "FP_RECPE_SPEC"
0022 },
0023 {
0024 "ArchStdEvent": "FP_CVT_SPEC"
0025 },
0026 {
0027 "ArchStdEvent": "ASE_SVE_INT_SPEC"
0028 },
0029 {
0030 "ArchStdEvent": "SVE_PRED_SPEC"
0031 },
0032 {
0033 "ArchStdEvent": "SVE_MOVPRFX_SPEC"
0034 },
0035 {
0036 "ArchStdEvent": "SVE_MOVPRFX_U_SPEC"
0037 },
0038 {
0039 "ArchStdEvent": "ASE_SVE_LD_SPEC"
0040 },
0041 {
0042 "ArchStdEvent": "ASE_SVE_ST_SPEC"
0043 },
0044 {
0045 "ArchStdEvent": "PRF_SPEC"
0046 },
0047 {
0048 "ArchStdEvent": "BASE_LD_REG_SPEC"
0049 },
0050 {
0051 "ArchStdEvent": "BASE_ST_REG_SPEC"
0052 },
0053 {
0054 "ArchStdEvent": "SVE_LDR_REG_SPEC"
0055 },
0056 {
0057 "ArchStdEvent": "SVE_STR_REG_SPEC"
0058 },
0059 {
0060 "ArchStdEvent": "SVE_LDR_PREG_SPEC"
0061 },
0062 {
0063 "ArchStdEvent": "SVE_STR_PREG_SPEC"
0064 },
0065 {
0066 "ArchStdEvent": "SVE_PRF_CONTIG_SPEC"
0067 },
0068 {
0069 "ArchStdEvent": "ASE_SVE_LD_MULTI_SPEC"
0070 },
0071 {
0072 "ArchStdEvent": "ASE_SVE_ST_MULTI_SPEC"
0073 },
0074 {
0075 "ArchStdEvent": "SVE_LD_GATHER_SPEC"
0076 },
0077 {
0078 "ArchStdEvent": "SVE_ST_SCATTER_SPEC"
0079 },
0080 {
0081 "ArchStdEvent": "SVE_PRF_GATHER_SPEC"
0082 },
0083 {
0084 "ArchStdEvent": "SVE_LDFF_SPEC"
0085 },
0086 {
0087 "ArchStdEvent": "FP_SCALE_OPS_SPEC"
0088 },
0089 {
0090 "ArchStdEvent": "FP_FIXED_OPS_SPEC"
0091 },
0092 {
0093 "ArchStdEvent": "FP_HP_SCALE_OPS_SPEC"
0094 },
0095 {
0096 "ArchStdEvent": "FP_HP_FIXED_OPS_SPEC"
0097 },
0098 {
0099 "ArchStdEvent": "FP_SP_SCALE_OPS_SPEC"
0100 },
0101 {
0102 "ArchStdEvent": "FP_SP_FIXED_OPS_SPEC"
0103 },
0104 {
0105 "ArchStdEvent": "FP_DP_SCALE_OPS_SPEC"
0106 },
0107 {
0108 "ArchStdEvent": "FP_DP_FIXED_OPS_SPEC"
0109 }
0110 ]
