0001 [
0002 {
0003 "ArchStdEvent": "L1D_CACHE_RD"
0004 },
0005 {
0006 "ArchStdEvent": "L1D_CACHE_WR"
0007 },
0008 {
0009 "ArchStdEvent": "L1D_CACHE_REFILL_RD"
0010 },
0011 {
0012 "ArchStdEvent": "L1D_CACHE_REFILL_WR"
0013 },
0014 {
0015 "ArchStdEvent": "L1D_CACHE_REFILL_INNER"
0016 },
0017 {
0018 "ArchStdEvent": "L1D_CACHE_REFILL_OUTER"
0019 },
0020 {
0021 "ArchStdEvent": "L1D_CACHE_WB_VICTIM"
0022 },
0023 {
0024 "ArchStdEvent": "L1D_CACHE_WB_CLEAN"
0025 },
0026 {
0027 "ArchStdEvent": "L1D_CACHE_INVAL"
0028 },
0029 {
0030 "ArchStdEvent": "L1D_TLB_REFILL_RD"
0031 },
0032 {
0033 "ArchStdEvent": "L1D_TLB_REFILL_WR"
0034 },
0035 {
0036 "ArchStdEvent": "L1D_TLB_RD"
0037 },
0038 {
0039 "ArchStdEvent": "L1D_TLB_WR"
0040 },
0041 {
0042 "ArchStdEvent": "L2D_TLB_REFILL_RD"
0043 },
0044 {
0045 "ArchStdEvent": "L2D_TLB_REFILL_WR"
0046 },
0047 {
0048 "ArchStdEvent": "L2D_TLB_RD"
0049 },
0050 {
0051 "ArchStdEvent": "L2D_TLB_WR"
0052 },
0053 {
0054 "ArchStdEvent": "BUS_ACCESS_RD"
0055 },
0056 {
0057 "ArchStdEvent": "BUS_ACCESS_WR"
0058 },
0059 {
0060 "ArchStdEvent": "MEM_ACCESS_RD"
0061 },
0062 {
0063 "ArchStdEvent": "MEM_ACCESS_WR"
0064 },
0065 {
0066 "ArchStdEvent": "UNALIGNED_LD_SPEC"
0067 },
0068 {
0069 "ArchStdEvent": "UNALIGNED_ST_SPEC"
0070 },
0071 {
0072 "ArchStdEvent": "UNALIGNED_LDST_SPEC"
0073 },
0074 {
0075 "ArchStdEvent": "EXC_UNDEF"
0076 },
0077 {
0078 "ArchStdEvent": "EXC_SVC"
0079 },
0080 {
0081 "ArchStdEvent": "EXC_PABORT"
0082 },
0083 {
0084 "ArchStdEvent": "EXC_DABORT"
0085 },
0086 {
0087 "ArchStdEvent": "EXC_IRQ"
0088 },
0089 {
0090 "ArchStdEvent": "EXC_FIQ"
0091 },
0092 {
0093 "ArchStdEvent": "EXC_SMC"
0094 },
0095 {
0096 "ArchStdEvent": "EXC_HVC"
0097 },
0098 {
0099 "ArchStdEvent": "EXC_TRAP_PABORT"
0100 },
0101 {
0102 "ArchStdEvent": "EXC_TRAP_DABORT"
0103 },
0104 {
0105 "ArchStdEvent": "EXC_TRAP_OTHER"
0106 },
0107 {
0108 "ArchStdEvent": "EXC_TRAP_IRQ"
0109 },
0110 {
0111 "ArchStdEvent": "EXC_TRAP_FIQ"
0112 }
0113 ]
