0001 [
0002 {
0003 "ArchStdEvent": "SW_INCR"
0004 },
0005 {
0006 "ArchStdEvent": "LD_RETIRED"
0007 },
0008 {
0009 "ArchStdEvent": "ST_RETIRED"
0010 },
0011 {
0012 "ArchStdEvent": "INST_RETIRED"
0013 },
0014 {
0015 "ArchStdEvent": "EXC_RETURN"
0016 },
0017 {
0018 "ArchStdEvent": "CID_WRITE_RETIRED"
0019 },
0020 {
0021 "ArchStdEvent": "PC_WRITE_RETIRED"
0022 },
0023 {
0024 "ArchStdEvent": "BR_IMMED_RETIRED"
0025 },
0026 {
0027 "ArchStdEvent": "BR_RETURN_RETIRED"
0028 },
0029 {
0030 "ArchStdEvent": "INST_SPEC"
0031 },
0032 {
0033 "ArchStdEvent": "TTBR_WRITE_RETIRED"
0034 },
0035 {
0036 "ArchStdEvent": "BR_RETIRED"
0037 },
0038 {
0039 "ArchStdEvent": "BR_MIS_PRED_RETIRED"
0040 },
0041 {
0042 "ArchStdEvent": "LD_SPEC"
0043 },
0044 {
0045 "ArchStdEvent": "ST_SPEC"
0046 },
0047 {
0048 "ArchStdEvent": "LDST_SPEC"
0049 },
0050 {
0051 "ArchStdEvent": "DP_SPEC"
0052 },
0053 {
0054 "ArchStdEvent": "ASE_SPEC"
0055 },
0056 {
0057 "ArchStdEvent": "VFP_SPEC"
0058 },
0059 {
0060 "ArchStdEvent": "CRYPTO_SPEC"
0061 },
0062 {
0063 "ArchStdEvent": "ISB_SPEC"
0064 }
0065 ]
