arm/cortex-a76-n1/instruction.json

0001 [
0002     {
0003         "ArchStdEvent": "SW_INCR"
0004     },
0005     {
0006         "PublicDescription": "This event counts all retired instructions, including those that fail their condition check.",
0007         "ArchStdEvent": "INST_RETIRED"
0008     },
0009     {
0010         "ArchStdEvent": "EXC_RETURN"
0011     },
0012     {
0013         "PublicDescription": "This event only counts writes to CONTEXTIDR in AArch32 state, and via the CONTEXTIDR_EL1 mnemonic in AArch64 state.",
0014         "ArchStdEvent": "CID_WRITE_RETIRED"
0015     },
0016     {
0017         "ArchStdEvent": "INST_SPEC"
0018     },
0019     {
0020         "PublicDescription": "This event only counts writes to TTBR0/TTBR1 in AArch32 state and TTBR0_EL1/TTBR1_EL1 in AArch64 state.",
0021         "ArchStdEvent": "TTBR_WRITE_RETIRED"
0022     },
0023     {
0024         "PublicDescription": "This event counts all branches, taken or not. This excludes exception entries, debug entries and CCFAIL branches.",
0025         "ArchStdEvent": "BR_RETIRED"
0026     },
0027     {
0028         "PublicDescription": "This event counts any branch counted by BR_RETIRED which is not correctly predicted and causes a pipeline flush.",
0029         "ArchStdEvent": "BR_MIS_PRED_RETIRED"
0030     },
0031     {
0032         "ArchStdEvent": "ASE_SPEC"
0033     },
0034     {
0035         "ArchStdEvent": "BR_IMMED_SPEC"
0036     },
0037     {
0038         "ArchStdEvent": "BR_INDIRECT_SPEC"
0039     },
0040     {
0041         "ArchStdEvent": "BR_RETURN_SPEC"
0042     },
0043     {
0044         "ArchStdEvent": "CRYPTO_SPEC"
0045     },
0046     {
0047         "ArchStdEvent": "DMB_SPEC"
0048     },
0049     {
0050         "ArchStdEvent": "DP_SPEC"
0051     },
0052     {
0053         "ArchStdEvent": "DSB_SPEC"
0054     },
0055     {
0056         "ArchStdEvent": "ISB_SPEC"
0057     },
0058     {
0059         "ArchStdEvent": "LDREX_SPEC"
0060     },
0061     {
0062         "ArchStdEvent": "LDST_SPEC"
0063     },
0064     {
0065         "ArchStdEvent": "LD_SPEC"
0066     },
0067     {
0068         "ArchStdEvent": "PC_WRITE_SPEC"
0069     },
0070     {
0071         "ArchStdEvent": "RC_LD_SPEC"
0072     },
0073     {
0074         "ArchStdEvent": "RC_ST_SPEC"
0075     },
0076     {
0077         "ArchStdEvent": "STREX_FAIL_SPEC"
0078     },
0079     {
0080         "ArchStdEvent": "STREX_PASS_SPEC"
0081     },
0082     {
0083         "ArchStdEvent": "STREX_SPEC"
0084     },
0085     {
0086         "ArchStdEvent": "ST_SPEC"
0087     },
0088     {
0089         "ArchStdEvent": "VFP_SPEC"
0090     }
0091 ]