0001 [
0002 {
0003 "PublicDescription": "The number of core clock cycles",
0004 "ArchStdEvent": "CPU_CYCLES",
0005 "BriefDescription": "The number of core clock cycles."
0006 },
0007 {
0008 "PublicDescription": "This event counts for every beat of data transferred over the data channels between the core and the SCU. If both read and write data beats are transferred on a given cycle, this event is counted twice on that cycle. This event counts the sum of BUS_ACCESS_RD and BUS_ACCESS_WR.",
0009 "ArchStdEvent": "BUS_ACCESS"
0010 },
0011 {
0012 "PublicDescription": "This event duplicates CPU_CYCLES.",
0013 "ArchStdEvent": "BUS_CYCLES"
0014 },
0015 {
0016 "ArchStdEvent": "BUS_ACCESS_RD"
0017 },
0018 {
0019 "ArchStdEvent": "BUS_ACCESS_WR"
0020 }
0021 ]
