0001 [
0002 {
0003 "ArchStdEvent": "L1I_CACHE_REFILL"
0004 },
0005 {
0006 "ArchStdEvent": "L1I_TLB_REFILL"
0007 },
0008 {
0009 "ArchStdEvent": "L1D_CACHE_REFILL"
0010 },
0011 {
0012 "ArchStdEvent": "L1D_CACHE"
0013 },
0014 {
0015 "ArchStdEvent": "L1D_TLB_REFILL"
0016 },
0017 {
0018 "ArchStdEvent": "L1I_CACHE"
0019 },
0020 {
0021 "ArchStdEvent": "L1D_CACHE_WB"
0022 },
0023 {
0024 "ArchStdEvent": "L2D_CACHE"
0025 },
0026 {
0027 "ArchStdEvent": "L2D_CACHE_REFILL"
0028 },
0029 {
0030 "ArchStdEvent": "L2D_CACHE_WB"
0031 },
0032 {
0033 "ArchStdEvent": "L1D_CACHE_RD"
0034 },
0035 {
0036 "ArchStdEvent": "L1D_CACHE_WR"
0037 },
0038 {
0039 "ArchStdEvent": "L2D_CACHE_RD"
0040 },
0041 {
0042 "ArchStdEvent": "L2D_CACHE_WR"
0043 },
0044 {
0045 "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
0046 },
0047 {
0048 "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
0049 },
0050 {
0051 "ArchStdEvent": "L2D_CACHE_INVAL"
0052 },
0053 {
0054 "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
0055 "EventCode": "0xC2",
0056 "EventName": "I_TAG_RAM_RD",
0057 "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
0058 },
0059 {
0060 "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
0061 "EventCode": "0xC3",
0062 "EventName": "I_DATA_RAM_RD",
0063 "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
0064 },
0065 {
0066 "PublicDescription": "Number of ways read in the instruction BTAC RAM",
0067 "EventCode": "0xC4",
0068 "EventName": "I_BTAC_RAM_RD",
0069 "BriefDescription": "Number of ways read in the instruction BTAC RAM"
0070 },
0071 {
0072 "PublicDescription": "Level 1 PLD TLB refill",
0073 "EventCode": "0xE7",
0074 "EventName": "PLD_UTLB_REFILL",
0075 "BriefDescription": "Level 1 PLD TLB refill"
0076 },
0077 {
0078 "PublicDescription": "Level 1 CP15 TLB refill",
0079 "EventCode": "0xE8",
0080 "EventName": "CP15_UTLB_REFILL",
0081 "BriefDescription": "Level 1 CP15 TLB refill"
0082 },
0083 {
0084 "PublicDescription": "Level 1 TLB flush",
0085 "EventCode": "0xE9",
0086 "EventName": "UTLB_FLUSH",
0087 "BriefDescription": "Level 1 TLB flush"
0088 },
0089 {
0090 "PublicDescription": "Level 2 TLB access",
0091 "EventCode": "0xEA",
0092 "EventName": "TLB_ACCESS",
0093 "BriefDescription": "Level 2 TLB access"
0094 },
0095 {
0096 "PublicDescription": "Level 2 TLB miss",
0097 "EventCode": "0xEB",
0098 "EventName": "TLB_MISS",
0099 "BriefDescription": "Level 2 TLB miss"
0100 },
0101 {
0102 "PublicDescription": "Data cache hit in itself due to VIPT aliasing",
0103 "EventCode": "0xEC",
0104 "EventName": "DCACHE_SELF_HIT_VIPT",
0105 "BriefDescription": "Data cache hit in itself due to VIPT aliasing"
0106 }
0107 ]
