0001 [
0002 {
0003 "ArchStdEvent": "STALL_FRONTEND"
0004 },
0005 {
0006 "ArchStdEvent": "STALL_BACKEND"
0007 },
0008 {
0009 "PublicDescription": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed",
0010 "EventCode": "0xE1",
0011 "EventName": "STALL_FRONTEND_CACHE",
0012 "BriefDescription": "No operation issued due to the frontend, cache miss.This event counts every cycle the DPU IQ is empty and there is an instruction cache miss being processed"
0013 },
0014 {
0015 "PublicDescription": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed",
0016 "EventCode": "0xE2",
0017 "EventName": "STALL_FRONTEND_TLB",
0018 "BriefDescription": "No operation issued due to the frontend, TLB miss.This event counts every cycle the DPU IQ is empty and there is an instruction L1 TLB miss being processed"
0019 },
0020 {
0021 "PublicDescription": "No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed",
0022 "EventCode": "0xE3",
0023 "EventName": "STALL_FRONTEND_PDERR",
0024 "BriefDescription": "No operation issued due to the frontend, pre-decode error.This event counts every cycle the DPU IQ is empty and there is a pre-decode error being processed"
0025 },
0026 {
0027 "PublicDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded",
0028 "EventCode": "0xE4",
0029 "EventName": "STALL_BACKEND_ILOCK",
0030 "BriefDescription": "No operation issued due to the backend interlock.This event counts every cycle that issue is stalled and there is an interlock. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded"
0031 },
0032 {
0033 "PublicDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded",
0034 "EventCode": "0xE5",
0035 "EventName": "STALL_BACKEND_ILOCK_AGU",
0036 "BriefDescription": "No operation issued due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there is an interlock that is due to a load/store instruction waiting for data to calculate the address in the AGU. Stall cycles due to a stall in Wr (typically awaiting load data) are excluded"
0037 },
0038 {
0039 "PublicDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded",
0040 "EventCode": "0xE6",
0041 "EventName": "STALL_BACKEND_ILOCK_FPU",
0042 "BriefDescription": "No operation issued due to the backend, interlock, FPU.This event counts every cycle that issue is stalled and there is an interlock that is due to an FPU/NEON instruction. Stall cycles due to a stall in the Wr stage (typically awaiting load data) are excluded"
0043 },
0044 {
0045 "PublicDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load",
0046 "EventCode": "0xE7",
0047 "EventName": "STALL_BACKEND_LD",
0048 "BriefDescription": "No operation issued due to the backend, load.This event counts every cycle there is a stall in the Wr stage due to a load"
0049 },
0050 {
0051 "PublicDescription": "No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store",
0052 "EventCode": "0xE8",
0053 "EventName": "STALL_BACKEND_ST",
0054 "BriefDescription": "No operation issued due to the backend, store.This event counts every cycle there is a stall in the Wr stage due to a store"
0055 },
0056 {
0057 "PublicDescription": "No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)",
0058 "EventCode": "0xE9",
0059 "EventName": "STALL_BACKEND_LD_CACHE",
0060 "BriefDescription": "No operation issued due to the backend, load, cache miss.This event counts every cycle there is a stall in the Wr stage due to a load which is waiting on data (due to missing the cache or being non-cacheable)"
0061 },
0062 {
0063 "PublicDescription": "No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB",
0064 "EventCode": "0xEA",
0065 "EventName": "STALL_BACKEND_LD_TLB",
0066 "BriefDescription": "No operation issued due to the backend, load, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a load which has missed in the L1 TLB"
0067 },
0068 {
0069 "PublicDescription": "No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full",
0070 "EventCode": "0xEB",
0071 "EventName": "STALL_BACKEND_ST_STB",
0072 "BriefDescription": "No operation issued due to the backend, store, STB full.This event counts every cycle there is a stall in the Wr stage due to a store which is waiting due to the STB being full"
0073 },
0074 {
0075 "PublicDescription": "No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB",
0076 "EventCode": "0xEC",
0077 "EventName": "STALL_BACKEND_ST_TLB",
0078 "BriefDescription": "No operation issued due to the backend, store, TLB miss.This event counts every cycle there is a stall in the Wr stage due to a store which has missed in the L1 TLB"
0079 }
0080 ]
