0001 [
0002 {
0003 "EventCode": "0xC7",
0004 "EventName": "STALL_SB_FULL",
0005 "BriefDescription": "Data Write operation that stalls the pipeline because the store buffer is full"
0006 },
0007 {
0008 "EventCode": "0xE0",
0009 "EventName": "OTHER_IQ_DEP_STALL",
0010 "BriefDescription": "Cycles that the DPU IQ is empty and that is not because of a recent micro-TLB miss, instruction cache miss or pre-decode error"
0011 },
0012 {
0013 "EventCode": "0xE1",
0014 "EventName": "IC_DEP_STALL",
0015 "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction cache miss being processed"
0016 },
0017 {
0018 "EventCode": "0xE2",
0019 "EventName": "IUTLB_DEP_STALL",
0020 "BriefDescription": "Cycles the DPU IQ is empty and there is an instruction micro-TLB miss being processed"
0021 },
0022 {
0023 "EventCode": "0xE3",
0024 "EventName": "DECODE_DEP_STALL",
0025 "BriefDescription": "Cycles the DPU IQ is empty and there is a pre-decode error being processed"
0026 },
0027 {
0028 "EventCode": "0xE4",
0029 "EventName": "OTHER_INTERLOCK_STALL",
0030 "BriefDescription": "Cycles there is an interlock other than Advanced SIMD/Floating-point instructions or load/store instruction"
0031 },
0032 {
0033 "EventCode": "0xE5",
0034 "EventName": "AGU_DEP_STALL",
0035 "BriefDescription": "Cycles there is an interlock for a load/store instruction waiting for data to calculate the address in the AGU"
0036 },
0037 {
0038 "EventCode": "0xE6",
0039 "EventName": "SIMD_DEP_STALL",
0040 "BriefDescription": "Cycles there is an interlock for an Advanced SIMD/Floating-point operation."
0041 },
0042 {
0043 "EventCode": "0xE7",
0044 "EventName": "LD_DEP_STALL",
0045 "BriefDescription": "Cycles there is a stall in the Wr stage because of a load miss"
0046 },
0047 {
0048 "EventCode": "0xE8",
0049 "EventName": "ST_DEP_STALL",
0050 "BriefDescription": "Cycles there is a stall in the Wr stage because of a store"
0051 }
0052 ]
