0001 [
0002 {
0003 "ArchStdEvent": "L1I_CACHE_REFILL"
0004 },
0005 {
0006 "ArchStdEvent": "L1I_TLB_REFILL"
0007 },
0008 {
0009 "ArchStdEvent": "L1D_CACHE_REFILL"
0010 },
0011 {
0012 "ArchStdEvent": "L1D_CACHE"
0013 },
0014 {
0015 "ArchStdEvent": "L1D_TLB_REFILL"
0016 },
0017 {
0018 "ArchStdEvent": "L1I_CACHE"
0019 },
0020 {
0021 "ArchStdEvent": "L1D_CACHE_WB"
0022 },
0023 {
0024 "ArchStdEvent": "L2D_CACHE"
0025 },
0026 {
0027 "ArchStdEvent": "L2D_CACHE_REFILL"
0028 },
0029 {
0030 "ArchStdEvent": "L2D_CACHE_WB"
0031 }
0032 ]
