0001 [
0002 {
0003 "ArchStdEvent": "L1D_CACHE_RD"
0004 },
0005 {
0006 "ArchStdEvent": "L1D_CACHE_WR"
0007 },
0008 {
0009 "ArchStdEvent": "L1D_CACHE_REFILL_RD"
0010 },
0011 {
0012 "ArchStdEvent": "L1D_CACHE_INVAL"
0013 },
0014 {
0015 "ArchStdEvent": "L1D_TLB_REFILL_RD"
0016 },
0017 {
0018 "ArchStdEvent": "L1D_TLB_REFILL_WR"
0019 },
0020 {
0021 "ArchStdEvent": "L2D_CACHE_RD"
0022 },
0023 {
0024 "ArchStdEvent": "L2D_CACHE_WR"
0025 },
0026 {
0027 "ArchStdEvent": "L2D_CACHE_REFILL_RD"
0028 },
0029 {
0030 "ArchStdEvent": "L2D_CACHE_REFILL_WR"
0031 },
0032 {
0033 "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
0034 },
0035 {
0036 "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
0037 },
0038 {
0039 "ArchStdEvent": "L2D_CACHE_INVAL"
0040 },
0041 {
0042 "ArchStdEvent": "L1I_CACHE_REFILL"
0043 },
0044 {
0045 "ArchStdEvent": "L1I_TLB_REFILL"
0046 },
0047 {
0048 "ArchStdEvent": "L1D_CACHE_REFILL"
0049 },
0050 {
0051 "ArchStdEvent": "L1D_CACHE"
0052 },
0053 {
0054 "ArchStdEvent": "L1D_TLB_REFILL"
0055 },
0056 {
0057 "ArchStdEvent": "L1I_CACHE"
0058 },
0059 {
0060 "ArchStdEvent": "L2D_CACHE"
0061 },
0062 {
0063 "ArchStdEvent": "L2D_CACHE_REFILL"
0064 },
0065 {
0066 "ArchStdEvent": "L2D_CACHE_WB"
0067 },
0068 {
0069 "PublicDescription": "This event counts any load or store operation which accesses the data L1 TLB",
0070 "ArchStdEvent": "L1D_TLB",
0071 "BriefDescription": "L1D TLB access"
0072 },
0073 {
0074 "PublicDescription": "This event counts any instruction fetch which accesses the instruction L1 TLB",
0075 "ArchStdEvent": "L1I_TLB"
0076 },
0077 {
0078 "PublicDescription": "Level 2 access to data TLB that caused a page table walk. This event counts on any data access which causes L2D_TLB_REFILL to count",
0079 "EventCode": "0x34",
0080 "EventName": "L2D_TLB_ACCESS",
0081 "BriefDescription": "L2D TLB access"
0082 },
0083 {
0084 "PublicDescription": "Level 2 access to instruciton TLB that caused a page table walk. This event counts on any instruciton access which causes L2I_TLB_REFILL to count",
0085 "EventCode": "0x35",
0086 "EventName": "L2I_TLB_ACCESS",
0087 "BriefDescription": "L2I TLB access"
0088 },
0089 {
0090 "PublicDescription": "Branch target buffer misprediction",
0091 "EventCode": "0x102",
0092 "EventName": "BTB_MIS_PRED",
0093 "BriefDescription": "BTB misprediction"
0094 },
0095 {
0096 "PublicDescription": "ITB miss",
0097 "EventCode": "0x103",
0098 "EventName": "ITB_MISS",
0099 "BriefDescription": "ITB miss"
0100 },
0101 {
0102 "PublicDescription": "DTB miss",
0103 "EventCode": "0x104",
0104 "EventName": "DTB_MISS",
0105 "BriefDescription": "DTB miss"
0106 },
0107 {
0108 "PublicDescription": "Level 1 data cache late miss",
0109 "EventCode": "0x105",
0110 "EventName": "L1D_CACHE_LATE_MISS",
0111 "BriefDescription": "L1D cache late miss"
0112 },
0113 {
0114 "PublicDescription": "Level 1 data cache prefetch request",
0115 "EventCode": "0x106",
0116 "EventName": "L1D_CACHE_PREFETCH",
0117 "BriefDescription": "L1D cache prefetch"
0118 },
0119 {
0120 "PublicDescription": "Level 2 data cache prefetch request",
0121 "EventCode": "0x107",
0122 "EventName": "L2D_CACHE_PREFETCH",
0123 "BriefDescription": "L2D cache prefetch"
0124 },
0125 {
0126 "PublicDescription": "Level 1 stage 2 TLB refill",
0127 "EventCode": "0x111",
0128 "EventName": "L1_STAGE2_TLB_REFILL",
0129 "BriefDescription": "L1 stage 2 TLB refill"
0130 },
0131 {
0132 "PublicDescription": "Page walk cache level-0 stage-1 hit",
0133 "EventCode": "0x112",
0134 "EventName": "PAGE_WALK_L0_STAGE1_HIT",
0135 "BriefDescription": "Page walk, L0 stage-1 hit"
0136 },
0137 {
0138 "PublicDescription": "Page walk cache level-1 stage-1 hit",
0139 "EventCode": "0x113",
0140 "EventName": "PAGE_WALK_L1_STAGE1_HIT",
0141 "BriefDescription": "Page walk, L1 stage-1 hit"
0142 },
0143 {
0144 "PublicDescription": "Page walk cache level-2 stage-1 hit",
0145 "EventCode": "0x114",
0146 "EventName": "PAGE_WALK_L2_STAGE1_HIT",
0147 "BriefDescription": "Page walk, L2 stage-1 hit"
0148 },
0149 {
0150 "PublicDescription": "Page walk cache level-1 stage-2 hit",
0151 "EventCode": "0x115",
0152 "EventName": "PAGE_WALK_L1_STAGE2_HIT",
0153 "BriefDescription": "Page walk, L1 stage-2 hit"
0154 },
0155 {
0156 "PublicDescription": "Page walk cache level-2 stage-2 hit",
0157 "EventCode": "0x116",
0158 "EventName": "PAGE_WALK_L2_STAGE2_HIT",
0159 "BriefDescription": "Page walk, L2 stage-2 hit"
0160 }
0161 ]
