include/nolibc/arch-arm.h

0001 /* SPDX-License-Identifier: LGPL-2.1 OR MIT */
0002 /*
0003  * ARM specific definitions for NOLIBC
0004  * Copyright (C) 2017-2022 Willy Tarreau <w@1wt.eu>
0005  */
0006
0007 #ifndef _NOLIBC_ARCH_ARM_H
0008 #define _NOLIBC_ARCH_ARM_H
0009
0010 /* O_* macros for fcntl/open are architecture-specific */
0011 #define O_RDONLY            0
0012 #define O_WRONLY            1
0013 #define O_RDWR              2
0014 #define O_CREAT          0x40
0015 #define O_EXCL           0x80
0016 #define O_NOCTTY        0x100
0017 #define O_TRUNC         0x200
0018 #define O_APPEND        0x400
0019 #define O_NONBLOCK      0x800
0020 #define O_DIRECTORY    0x4000
0021
0022 /* The struct returned by the stat() syscall, 32-bit only, the syscall returns
0023  * exactly 56 bytes (stops before the unused array). In big endian, the format
0024  * differs as devices are returned as short only.
0025  */
0026 struct sys_stat_struct {
0027 #if defined(__ARMEB__)
0028     unsigned short st_dev;
0029     unsigned short __pad1;
0030 #else
0031     unsigned long  st_dev;
0032 #endif
0033     unsigned long  st_ino;
0034     unsigned short st_mode;
0035     unsigned short st_nlink;
0036     unsigned short st_uid;
0037     unsigned short st_gid;
0038
0039 #if defined(__ARMEB__)
0040     unsigned short st_rdev;
0041     unsigned short __pad2;
0042 #else
0043     unsigned long  st_rdev;
0044 #endif
0045     unsigned long  st_size;
0046     unsigned long  st_blksize;
0047     unsigned long  st_blocks;
0048
0049     unsigned long  st_atime;
0050     unsigned long  st_atime_nsec;
0051     unsigned long  st_mtime;
0052     unsigned long  st_mtime_nsec;
0053
0054     unsigned long  st_ctime;
0055     unsigned long  st_ctime_nsec;
0056     unsigned long  __unused[2];
0057 };
0058
0059 /* Syscalls for ARM in ARM or Thumb modes :
0060  *   - registers are 32-bit
0061  *   - stack is 8-byte aligned
0062  *     ( http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/ka4127.html)
0063  *   - syscall number is passed in r7
0064  *   - arguments are in r0, r1, r2, r3, r4, r5
0065  *   - the system call is performed by calling svc #0
0066  *   - syscall return comes in r0.
0067  *   - only lr is clobbered.
0068  *   - the arguments are cast to long and assigned into the target registers
0069  *     which are then simply passed as registers to the asm code, so that we
0070  *     don't have to experience issues with register constraints.
0071  *   - the syscall number is always specified last in order to allow to force
0072  *     some registers before (gcc refuses a %-register at the last position).
0073  *
0074  * Also, ARM supports the old_select syscall if newselect is not available
0075  */
0076 #define __ARCH_WANT_SYS_OLD_SELECT
0077
0078 #define my_syscall0(num)                                                      \
0079 ({                                                                            \
0080     register long _num __asm__ ("r7") = (num);                            \
0081     register long _arg1 __asm__ ("r0");                                   \
0082                                                                           \
0083     __asm__  volatile (                                                   \
0084         "svc #0\n"                                                    \
0085         : "=r"(_arg1)                                                 \
0086         : "r"(_num)                                                   \
0087         : "memory", "cc", "lr"                                        \
0088     );                                                                    \
0089     _arg1;                                                                \
0090 })
0091
0092 #define my_syscall1(num, arg1)                                                \
0093 ({                                                                            \
0094     register long _num __asm__ ("r7") = (num);                            \
0095     register long _arg1 __asm__ ("r0") = (long)(arg1);                    \
0096                                                                           \
0097     __asm__  volatile (                                                   \
0098         "svc #0\n"                                                    \
0099         : "=r"(_arg1)                                                 \
0100         : "r"(_arg1),                                                 \
0101           "r"(_num)                                                   \
0102         : "memory", "cc", "lr"                                        \
0103     );                                                                    \
0104     _arg1;                                                                \
0105 })
0106
0107 #define my_syscall2(num, arg1, arg2)                                          \
0108 ({                                                                            \
0109     register long _num __asm__ ("r7") = (num);                            \
0110     register long _arg1 __asm__ ("r0") = (long)(arg1);                    \
0111     register long _arg2 __asm__ ("r1") = (long)(arg2);                    \
0112                                                                           \
0113     __asm__  volatile (                                                   \
0114         "svc #0\n"                                                    \
0115         : "=r"(_arg1)                                                 \
0116         : "r"(_arg1), "r"(_arg2),                                     \
0117           "r"(_num)                                                   \
0118         : "memory", "cc", "lr"                                        \
0119     );                                                                    \
0120     _arg1;                                                                \
0121 })
0122
0123 #define my_syscall3(num, arg1, arg2, arg3)                                    \
0124 ({                                                                            \
0125     register long _num __asm__ ("r7") = (num);                            \
0126     register long _arg1 __asm__ ("r0") = (long)(arg1);                    \
0127     register long _arg2 __asm__ ("r1") = (long)(arg2);                    \
0128     register long _arg3 __asm__ ("r2") = (long)(arg3);                    \
0129                                                                           \
0130     __asm__  volatile (                                                   \
0131         "svc #0\n"                                                    \
0132         : "=r"(_arg1)                                                 \
0133         : "r"(_arg1), "r"(_arg2), "r"(_arg3),                         \
0134           "r"(_num)                                                   \
0135         : "memory", "cc", "lr"                                        \
0136     );                                                                    \
0137     _arg1;                                                                \
0138 })
0139
0140 #define my_syscall4(num, arg1, arg2, arg3, arg4)                              \
0141 ({                                                                            \
0142     register long _num __asm__ ("r7") = (num);                            \
0143     register long _arg1 __asm__ ("r0") = (long)(arg1);                    \
0144     register long _arg2 __asm__ ("r1") = (long)(arg2);                    \
0145     register long _arg3 __asm__ ("r2") = (long)(arg3);                    \
0146     register long _arg4 __asm__ ("r3") = (long)(arg4);                    \
0147                                                                           \
0148     __asm__  volatile (                                                   \
0149         "svc #0\n"                                                    \
0150         : "=r"(_arg1)                                                 \
0151         : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4),             \
0152           "r"(_num)                                                   \
0153         : "memory", "cc", "lr"                                        \
0154     );                                                                    \
0155     _arg1;                                                                \
0156 })
0157
0158 #define my_syscall5(num, arg1, arg2, arg3, arg4, arg5)                        \
0159 ({                                                                            \
0160     register long _num __asm__ ("r7") = (num);                            \
0161     register long _arg1 __asm__ ("r0") = (long)(arg1);                    \
0162     register long _arg2 __asm__ ("r1") = (long)(arg2);                    \
0163     register long _arg3 __asm__ ("r2") = (long)(arg3);                    \
0164     register long _arg4 __asm__ ("r3") = (long)(arg4);                    \
0165     register long _arg5 __asm__ ("r4") = (long)(arg5);                    \
0166                                                                           \
0167     __asm__  volatile (                                                   \
0168         "svc #0\n"                                                    \
0169         : "=r" (_arg1)                                                \
0170         : "r"(_arg1), "r"(_arg2), "r"(_arg3), "r"(_arg4), "r"(_arg5), \
0171           "r"(_num)                                                   \
0172         : "memory", "cc", "lr"                                        \
0173     );                                                                    \
0174     _arg1;                                                                \
0175 })
0176
0177 /* startup code */
0178 __asm__ (".section .text\n"
0179     ".weak _start\n"
0180     "_start:\n"
0181 #if defined(__THUMBEB__) || defined(__THUMBEL__)
0182     /* We enter here in 32-bit mode but if some previous functions were in
0183      * 16-bit mode, the assembler cannot know, so we need to tell it we're in
0184      * 32-bit now, then switch to 16-bit (is there a better way to do it than
0185      * adding 1 by hand ?) and tell the asm we're now in 16-bit mode so that
0186      * it generates correct instructions. Note that we do not support thumb1.
0187      */
0188     ".code 32\n"
0189     "add     r0, pc, #1\n"
0190     "bx      r0\n"
0191     ".code 16\n"
0192 #endif
0193     "pop {%r0}\n"                 // argc was in the stack
0194     "mov %r1, %sp\n"              // argv = sp
0195     "add %r2, %r1, %r0, lsl #2\n" // envp = argv + 4*argc ...
0196     "add %r2, %r2, $4\n"          //        ... + 4
0197     "and %r3, %r1, $-8\n"         // AAPCS : sp must be 8-byte aligned in the
0198     "mov %sp, %r3\n"              //         callee, an bl doesn't push (lr=pc)
0199     "bl main\n"                   // main() returns the status code, we'll exit with it.
0200     "movs r7, $1\n"               // NR_exit == 1
0201     "svc $0x00\n"
0202     "");
0203
0204 #endif // _NOLIBC_ARCH_ARM_H