0001 # The basic row format is:
0002 # LEAF, SUBLEAF, register_name, bits, short_name, long_description
0003
0004 # Leaf 00H
0005 0, 0, EAX, 31:0, max_basic_leafs, Max input value for supported subleafs
0006
0007 # Leaf 01H
0008 1, 0, EAX, 3:0, stepping, Stepping ID
0009 1, 0, EAX, 7:4, model, Model
0010 1, 0, EAX, 11:8, family, Family ID
0011 1, 0, EAX, 13:12, processor, Processor Type
0012 1, 0, EAX, 19:16, model_ext, Extended Model ID
0013 1, 0, EAX, 27:20, family_ext, Extended Family ID
0014
0015 1, 0, EBX, 7:0, brand, Brand Index
0016 1, 0, EBX, 15:8, clflush_size, CLFLUSH line size (value * 8) in bytes
0017 1, 0, EBX, 23:16, max_cpu_id, Maxim number of addressable logic cpu in this package
0018 1, 0, EBX, 31:24, apic_id, Initial APIC ID
0019
0020 1, 0, ECX, 0, sse3, Streaming SIMD Extensions 3(SSE3)
0021 1, 0, ECX, 1, pclmulqdq, PCLMULQDQ instruction supported
0022 1, 0, ECX, 2, dtes64, DS area uses 64-bit layout
0023 1, 0, ECX, 3, mwait, MONITOR/MWAIT supported
0024 1, 0, ECX, 4, ds_cpl, CPL Qualified Debug Store which allows for branch message storage qualified by CPL
0025 1, 0, ECX, 5, vmx, Virtual Machine Extensions supported
0026 1, 0, ECX, 6, smx, Safer Mode Extension supported
0027 1, 0, ECX, 7, eist, Enhanced Intel SpeedStep Technology
0028 1, 0, ECX, 8, tm2, Thermal Monitor 2
0029 1, 0, ECX, 9, ssse3, Supplemental Streaming SIMD Extensions 3 (SSSE3)
0030 1, 0, ECX, 10, l1_ctx_id, L1 data cache could be set to either adaptive mode or shared mode (check IA32_MISC_ENABLE bit 24 definition)
0031 1, 0, ECX, 11, sdbg, IA32_DEBUG_INTERFACE MSR for silicon debug supported
0032 1, 0, ECX, 12, fma, FMA extensions using YMM state supported
0033 1, 0, ECX, 13, cmpxchg16b, 'CMPXCHG16B - Compare and Exchange Bytes' supported
0034 1, 0, ECX, 14, xtpr_update, xTPR Update Control supported
0035 1, 0, ECX, 15, pdcm, Perfmon and Debug Capability present
0036 1, 0, ECX, 17, pcid, Process-Context Identifiers feature present
0037 1, 0, ECX, 18, dca, Prefetching data from a memory mapped device supported
0038 1, 0, ECX, 19, sse4_1, SSE4.1 feature present
0039 1, 0, ECX, 20, sse4_2, SSE4.2 feature present
0040 1, 0, ECX, 21, x2apic, x2APIC supported
0041 1, 0, ECX, 22, movbe, MOVBE instruction supported
0042 1, 0, ECX, 23, popcnt, POPCNT instruction supported
0043 1, 0, ECX, 24, tsc_deadline_timer, LAPIC supports one-shot operation using a TSC deadline value
0044 1, 0, ECX, 25, aesni, AESNI instruction supported
0045 1, 0, ECX, 26, xsave, XSAVE/XRSTOR processor extended states (XSETBV/XGETBV/XCR0)
0046 1, 0, ECX, 27, osxsave, OS has set CR4.OSXSAVE bit to enable XSETBV/XGETBV/XCR0
0047 1, 0, ECX, 28, avx, AVX instruction supported
0048 1, 0, ECX, 29, f16c, 16-bit floating-point conversion instruction supported
0049 1, 0, ECX, 30, rdrand, RDRAND instruction supported
0050
0051 1, 0, EDX, 0, fpu, x87 FPU on chip
0052 1, 0, EDX, 1, vme, Virtual-8086 Mode Enhancement
0053 1, 0, EDX, 2, de, Debugging Extensions
0054 1, 0, EDX, 3, pse, Page Size Extensions
0055 1, 0, EDX, 4, tsc, Time Stamp Counter
0056 1, 0, EDX, 5, msr, RDMSR and WRMSR Support
0057 1, 0, EDX, 6, pae, Physical Address Extensions
0058 1, 0, EDX, 7, mce, Machine Check Exception
0059 1, 0, EDX, 8, cx8, CMPXCHG8B instr
0060 1, 0, EDX, 9, apic, APIC on Chip
0061 1, 0, EDX, 11, sep, SYSENTER and SYSEXIT instrs
0062 1, 0, EDX, 12, mtrr, Memory Type Range Registers
0063 1, 0, EDX, 13, pge, Page Global Bit
0064 1, 0, EDX, 14, mca, Machine Check Architecture
0065 1, 0, EDX, 15, cmov, Conditional Move Instrs
0066 1, 0, EDX, 16, pat, Page Attribute Table
0067 1, 0, EDX, 17, pse36, 36-Bit Page Size Extension
0068 1, 0, EDX, 18, psn, Processor Serial Number
0069 1, 0, EDX, 19, clflush, CLFLUSH instr
0070 # 1, 0, EDX, 20,
0071 1, 0, EDX, 21, ds, Debug Store
0072 1, 0, EDX, 22, acpi, Thermal Monitor and Software Controlled Clock Facilities
0073 1, 0, EDX, 23, mmx, Intel MMX Technology
0074 1, 0, EDX, 24, fxsr, XSAVE and FXRSTOR Instrs
0075 1, 0, EDX, 25, sse, SSE
0076 1, 0, EDX, 26, sse2, SSE2
0077 1, 0, EDX, 27, ss, Self Snoop
0078 1, 0, EDX, 28, hit, Max APIC IDs
0079 1, 0, EDX, 29, tm, Thermal Monitor
0080 # 1, 0, EDX, 30,
0081 1, 0, EDX, 31, pbe, Pending Break Enable
0082
0083 # Leaf 02H
0084 # cache and TLB descriptor info
0085
0086 # Leaf 03H
0087 # Precessor Serial Number, introduced on Pentium III, not valid for
0088 # latest models
0089
0090 # Leaf 04H
0091 # thread/core and cache topology
0092 4, 0, EAX, 4:0, cache_type, Cache type like instr/data or unified
0093 4, 0, EAX, 7:5, cache_level, Cache Level (starts at 1)
0094 4, 0, EAX, 8, cache_self_init, Cache Self Initialization
0095 4, 0, EAX, 9, fully_associate, Fully Associative cache
0096 # 4, 0, EAX, 13:10, resvd, resvd
0097 4, 0, EAX, 25:14, max_logical_id, Max number of addressable IDs for logical processors sharing the cache
0098 4, 0, EAX, 31:26, max_phy_id, Max number of addressable IDs for processors in phy package
0099
0100 4, 0, EBX, 11:0, cache_linesize, Size of a cache line in bytes
0101 4, 0, EBX, 21:12, cache_partition, Physical Line partitions
0102 4, 0, EBX, 31:22, cache_ways, Ways of associativity
0103 4, 0, ECX, 31:0, cache_sets, Number of Sets - 1
0104 4, 0, EDX, 0, c_wbinvd, 1 means WBINVD/INVD is not ganranteed to act upon lower level caches of non-originating threads sharing this cache
0105 4, 0, EDX, 1, c_incl, Whether cache is inclusive of lower cache level
0106 4, 0, EDX, 2, c_comp_index, Complex Cache Indexing
0107
0108 # Leaf 05H
0109 # MONITOR/MWAIT
0110 5, 0, EAX, 15:0, min_mon_size, Smallest monitor line size in bytes
0111 5, 0, EBX, 15:0, max_mon_size, Largest monitor line size in bytes
0112 5, 0, ECX, 0, mwait_ext, Enum of Monitor-Mwait extensions supported
0113 5, 0, ECX, 1, mwait_irq_break, Largest monitor line size in bytes
0114 5, 0, EDX, 3:0, c0_sub_stats, Number of C0* sub C-states supported using MWAIT
0115 5, 0, EDX, 7:4, c1_sub_stats, Number of C1* sub C-states supported using MWAIT
0116 5, 0, EDX, 11:8, c2_sub_stats, Number of C2* sub C-states supported using MWAIT
0117 5, 0, EDX, 15:12, c3_sub_stats, Number of C3* sub C-states supported using MWAIT
0118 5, 0, EDX, 19:16, c4_sub_stats, Number of C4* sub C-states supported using MWAIT
0119 5, 0, EDX, 23:20, c5_sub_stats, Number of C5* sub C-states supported using MWAIT
0120 5, 0, EDX, 27:24, c6_sub_stats, Number of C6* sub C-states supported using MWAIT
0121 5, 0, EDX, 31:28, c7_sub_stats, Number of C7* sub C-states supported using MWAIT
0122
0123 # Leaf 06H
0124 # Thermal & Power Management
0125
0126 6, 0, EAX, 0, dig_temp, Digital temperature sensor supported
0127 6, 0, EAX, 1, turbo, Intel Turbo Boost
0128 6, 0, EAX, 2, arat, Always running APIC timer
0129 # 6, 0, EAX, 3, resv, Reserved
0130 6, 0, EAX, 4, pln, Power limit notifications supported
0131 6, 0, EAX, 5, ecmd, Clock modulation duty cycle extension supported
0132 6, 0, EAX, 6, ptm, Package thermal management supported
0133 6, 0, EAX, 7, hwp, HWP base register
0134 6, 0, EAX, 8, hwp_notify, HWP notification
0135 6, 0, EAX, 9, hwp_act_window, HWP activity window
0136 6, 0, EAX, 10, hwp_energy, HWP energy performance preference
0137 6, 0, EAX, 11, hwp_pkg_req, HWP package level request
0138 # 6, 0, EAX, 12, resv, Reserved
0139 6, 0, EAX, 13, hdc, HDC base registers supported
0140 6, 0, EAX, 14, turbo3, Turbo Boost Max 3.0
0141 6, 0, EAX, 15, hwp_cap, Highest Performance change supported
0142 6, 0, EAX, 16, hwp_peci, HWP PECI override is supported
0143 6, 0, EAX, 17, hwp_flex, Flexible HWP is supported
0144 6, 0, EAX, 18, hwp_fast, Fast access mode for the IA32_HWP_REQUEST MSR is supported
0145 # 6, 0, EAX, 19, resv, Reserved
0146 6, 0, EAX, 20, hwp_ignr, Ignoring Idle Logical Processor HWP request is supported
0147
0148 6, 0, EBX, 3:0, therm_irq_thresh, Number of Interrupt Thresholds in Digital Thermal Sensor
0149 6, 0, ECX, 0, aperfmperf, Presence of IA32_MPERF and IA32_APERF
0150 6, 0, ECX, 3, energ_bias, Performance-energy bias preference supported
0151
0152 # Leaf 07H
0153 # ECX == 0
0154 # AVX512 refers to https://en.wikipedia.org/wiki/AVX-512
0155 # XXX: Do we really need to enumerate each and every AVX512 sub features
0156
0157 7, 0, EBX, 0, fsgsbase, RDFSBASE/RDGSBASE/WRFSBASE/WRGSBASE supported
0158 7, 0, EBX, 1, tsc_adjust, TSC_ADJUST MSR supported
0159 7, 0, EBX, 2, sgx, Software Guard Extensions
0160 7, 0, EBX, 3, bmi1, BMI1
0161 7, 0, EBX, 4, hle, Hardware Lock Elision
0162 7, 0, EBX, 5, avx2, AVX2
0163 # 7, 0, EBX, 6, fdp_excp_only, x87 FPU Data Pointer updated only on x87 exceptions
0164 7, 0, EBX, 7, smep, Supervisor-Mode Execution Prevention
0165 7, 0, EBX, 8, bmi2, BMI2
0166 7, 0, EBX, 9, rep_movsb, Enhanced REP MOVSB/STOSB
0167 7, 0, EBX, 10, invpcid, INVPCID instruction
0168 7, 0, EBX, 11, rtm, Restricted Transactional Memory
0169 7, 0, EBX, 12, rdt_m, Intel RDT Monitoring capability
0170 7, 0, EBX, 13, depc_fpu_cs_ds, Deprecates FPU CS and FPU DS
0171 7, 0, EBX, 14, mpx, Memory Protection Extensions
0172 7, 0, EBX, 15, rdt_a, Intel RDT Allocation capability
0173 7, 0, EBX, 16, avx512f, AVX512 Foundation instr
0174 7, 0, EBX, 17, avx512dq, AVX512 Double and Quadword AVX512 instr
0175 7, 0, EBX, 18, rdseed, RDSEED instr
0176 7, 0, EBX, 19, adx, ADX instr
0177 7, 0, EBX, 20, smap, Supervisor Mode Access Prevention
0178 7, 0, EBX, 21, avx512ifma, AVX512 Integer Fused Multiply Add
0179 # 7, 0, EBX, 22, resvd, resvd
0180 7, 0, EBX, 23, clflushopt, CLFLUSHOPT instr
0181 7, 0, EBX, 24, clwb, CLWB instr
0182 7, 0, EBX, 25, intel_pt, Intel Processor Trace instr
0183 7, 0, EBX, 26, avx512pf, Prefetch
0184 7, 0, EBX, 27, avx512er, AVX512 Exponent Reciproca instr
0185 7, 0, EBX, 28, avx512cd, AVX512 Conflict Detection instr
0186 7, 0, EBX, 29, sha, Intel Secure Hash Algorithm Extensions instr
0187 7, 0, EBX, 26, avx512bw, AVX512 Byte & Word instr
0188 7, 0, EBX, 28, avx512vl, AVX512 Vector Length Extentions (VL)
0189 7, 0, ECX, 0, prefetchwt1, X
0190 7, 0, ECX, 1, avx512vbmi, AVX512 Vector Byte Manipulation Instructions
0191 7, 0, ECX, 2, umip, User-mode Instruction Prevention
0192
0193 7, 0, ECX, 3, pku, Protection Keys for User-mode pages
0194 7, 0, ECX, 4, ospke, CR4 PKE set to enable protection keys
0195 # 7, 0, ECX, 16:5, resvd, resvd
0196 7, 0, ECX, 21:17, mawau, The value of MAWAU used by the BNDLDX and BNDSTX instructions in 64-bit mode
0197 7, 0, ECX, 22, rdpid, RDPID and IA32_TSC_AUX
0198 # 7, 0, ECX, 29:23, resvd, resvd
0199 7, 0, ECX, 30, sgx_lc, SGX Launch Configuration
0200 # 7, 0, ECX, 31, resvd, resvd
0201
0202 # Leaf 08H
0203 #
0204
0205
0206 # Leaf 09H
0207 # Direct Cache Access (DCA) information
0208 9, 0, ECX, 31:0, dca_cap, The value of IA32_PLATFORM_DCA_CAP
0209
0210 # Leaf 0AH
0211 # Architectural Performance Monitoring
0212 #
0213 # Do we really need to print out the PMU related stuff?
0214 # Does normal user really care about it?
0215 #
0216 0xA, 0, EAX, 7:0, pmu_ver, Performance Monitoring Unit version
0217 0xA, 0, EAX, 15:8, pmu_gp_cnt_num, Numer of general-purose PMU counters per logical CPU
0218 0xA, 0, EAX, 23:16, pmu_cnt_bits, Bit wideth of PMU counter
0219 0xA, 0, EAX, 31:24, pmu_ebx_bits, Length of EBX bit vector to enumerate PMU events
0220
0221 0xA, 0, EBX, 0, pmu_no_core_cycle_evt, Core cycle event not available
0222 0xA, 0, EBX, 1, pmu_no_instr_ret_evt, Instruction retired event not available
0223 0xA, 0, EBX, 2, pmu_no_ref_cycle_evt, Reference cycles event not available
0224 0xA, 0, EBX, 3, pmu_no_llc_ref_evt, Last-level cache reference event not available
0225 0xA, 0, EBX, 4, pmu_no_llc_mis_evt, Last-level cache misses event not available
0226 0xA, 0, EBX, 5, pmu_no_br_instr_ret_evt, Branch instruction retired event not available
0227 0xA, 0, EBX, 6, pmu_no_br_mispredict_evt, Branch mispredict retired event not available
0228
0229 0xA, 0, ECX, 4:0, pmu_fixed_cnt_num, Performance Monitoring Unit version
0230 0xA, 0, ECX, 12:5, pmu_fixed_cnt_bits, Numer of PMU counters per logical CPU
0231
0232 # Leaf 0BH
0233 # Extended Topology Enumeration Leaf
0234 #
0235
0236 0xB, 0, EAX, 4:0, id_shift, Number of bits to shift right on x2APIC ID to get a unique topology ID of the next level type
0237 0xB, 0, EBX, 15:0, cpu_nr, Number of logical processors at this level type
0238 0xB, 0, ECX, 15:8, lvl_type, 0-Invalid 1-SMT 2-Core
0239 0xB, 0, EDX, 31:0, x2apic_id, x2APIC ID the current logical processor
0240
0241
0242 # Leaf 0DH
0243 # Processor Extended State
0244
0245 0xD, 0, EAX, 0, x87, X87 state
0246 0xD, 0, EAX, 1, sse, SSE state
0247 0xD, 0, EAX, 2, avx, AVX state
0248 0xD, 0, EAX, 4:3, mpx, MPX state
0249 0xD, 0, EAX, 7:5, avx512, AVX-512 state
0250 0xD, 0, EAX, 9, pkru, PKRU state
0251
0252 0xD, 0, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
0253 0xD, 0, ECX, 31:0, max_sz_xsave, Maximum size (bytes) of the XSAVE/XRSTOR save area
0254
0255 0xD, 1, EAX, 0, xsaveopt, XSAVEOPT available
0256 0xD, 1, EAX, 1, xsavec, XSAVEC and compacted form supported
0257 0xD, 1, EAX, 2, xgetbv, XGETBV supported
0258 0xD, 1, EAX, 3, xsaves, XSAVES/XRSTORS and IA32_XSS supported
0259
0260 0xD, 1, EBX, 31:0, max_sz_xcr0, Maximum size (bytes) required by enabled features in XCR0
0261 0xD, 1, ECX, 8, pt, PT state
0262 0xD, 1, ECX, 11, cet_usr, CET user state
0263 0xD, 1, ECX, 12, cet_supv, CET supervisor state
0264 0xD, 1, ECX, 13, hdc, HDC state
0265 0xD, 1, ECX, 16, hwp, HWP state
0266
0267 # Leaf 0FH
0268 # Intel RDT Monitoring
0269
0270 0xF, 0, EBX, 31:0, rmid_range, Maximum range (zero-based) of RMID within this physical processor of all types
0271 0xF, 0, EDX, 1, l3c_rdt_mon, L3 Cache RDT Monitoring supported
0272
0273 0xF, 1, ECX, 31:0, rmid_range, Maximum range (zero-based) of RMID of this types
0274 0xF, 1, EDX, 0, l3c_ocp_mon, L3 Cache occupancy Monitoring supported
0275 0xF, 1, EDX, 1, l3c_tbw_mon, L3 Cache Total Bandwidth Monitoring supported
0276 0xF, 1, EDX, 2, l3c_lbw_mon, L3 Cache Local Bandwidth Monitoring supported
0277
0278 # Leaf 10H
0279 # Intel RDT Allocation
0280
0281 0x10, 0, EBX, 1, l3c_rdt_alloc, L3 Cache Allocation supported
0282 0x10, 0, EBX, 2, l2c_rdt_alloc, L2 Cache Allocation supported
0283 0x10, 0, EBX, 3, mem_bw_alloc, Memory Bandwidth Allocation supported
0284
0285
0286 # Leaf 12H
0287 # SGX Capability
0288 #
0289 # Some detailed SGX features not added yet
0290
0291 0x12, 0, EAX, 0, sgx1, L3 Cache Allocation supported
0292 0x12, 1, EAX, 0, sgx2, L3 Cache Allocation supported
0293
0294
0295 # Leaf 14H
0296 # Intel Processor Tracer
0297 #
0298
0299 # Leaf 15H
0300 # Time Stamp Counter and Nominal Core Crystal Clock Information
0301
0302 0x15, 0, EAX, 31:0, tsc_denominator, The denominator of the TSC/”core crystal clock” ratio
0303 0x15, 0, EBX, 31:0, tsc_numerator, The numerator of the TSC/”core crystal clock” ratio
0304 0x15, 0, ECX, 31:0, nom_freq, Nominal frequency of the core crystal clock in Hz
0305
0306 # Leaf 16H
0307 # Processor Frequency Information
0308
0309 0x16, 0, EAX, 15:0, cpu_base_freq, Processor Base Frequency in MHz
0310 0x16, 0, EBX, 15:0, cpu_max_freq, Maximum Frequency in MHz
0311 0x16, 0, ECX, 15:0, bus_freq, Bus (Reference) Frequency in MHz
0312
0313 # Leaf 17H
0314 # System-On-Chip Vendor Attribute
0315
0316 0x17, 0, EAX, 31:0, max_socid, Maximum input value of supported sub-leaf
0317 0x17, 0, EBX, 15:0, soc_vid, SOC Vendor ID
0318 0x17, 0, EBX, 16, std_vid, SOC Vendor ID is assigned via an industry standard scheme
0319 0x17, 0, ECX, 31:0, soc_pid, SOC Project ID assigned by vendor
0320 0x17, 0, EDX, 31:0, soc_sid, SOC Stepping ID
0321
0322 # Leaf 18H
0323 # Deterministic Address Translation Parameters
0324
0325
0326 # Leaf 19H
0327 # Key Locker Leaf
0328
0329
0330 # Leaf 1AH
0331 # Hybrid Information
0332
0333 0x1A, 0, EAX, 31:24, core_type, 20H-Intel_Atom 40H-Intel_Core
0334
0335
0336 # Leaf 1FH
0337 # V2 Extended Topology - A preferred superset to leaf 0BH
0338
0339
0340 # According to SDM
0341 # 40000000H - 4FFFFFFFH is invalid range
0342
0343
0344 # Leaf 80000001H
0345 # Extended Processor Signature and Feature Bits
0346
0347 0x80000001, 0, ECX, 0, lahf_lm, LAHF/SAHF available in 64-bit mode
0348 0x80000001, 0, ECX, 5, lzcnt, LZCNT
0349 0x80000001, 0, ECX, 8, prefetchw, PREFETCHW
0350
0351 0x80000001, 0, EDX, 11, sysret, SYSCALL/SYSRET supported
0352 0x80000001, 0, EDX, 20, exec_dis, Execute Disable Bit available
0353 0x80000001, 0, EDX, 26, 1gb_page, 1GB page supported
0354 0x80000001, 0, EDX, 27, rdtscp, RDTSCP and IA32_TSC_AUX are available
0355 #0x80000001, 0, EDX, 29, 64b, 64b Architecture supported
0356
0357 # Leaf 80000002H/80000003H/80000004H
0358 # Processor Brand String
0359
0360 # Leaf 80000005H
0361 # Reserved
0362
0363 # Leaf 80000006H
0364 # Extended L2 Cache Features
0365
0366 0x80000006, 0, ECX, 7:0, clsize, Cache Line size in bytes
0367 0x80000006, 0, ECX, 15:12, l2c_assoc, L2 Associativity
0368 0x80000006, 0, ECX, 31:16, csize, Cache size in 1K units
0369
0370
0371 # Leaf 80000007H
0372
0373 0x80000007, 0, EDX, 8, nonstop_tsc, Invariant TSC available
0374
0375
0376 # Leaf 80000008H
0377
0378 0x80000008, 0, EAX, 7:0, phy_adr_bits, Physical Address Bits
0379 0x80000008, 0, EAX, 15:8, lnr_adr_bits, Linear Address Bits
0380 0x80000007, 0, EBX, 9, wbnoinvd, WBNOINVD
0381
0382 # 0x8000001E
0383 # EAX: Extended APIC ID
0384 0x8000001E, 0, EAX, 31:0, extended_apic_id, Extended APIC ID
0385 # EBX: Core Identifiers
0386 0x8000001E, 0, EBX, 7:0, core_id, Identifies the logical core ID
0387 0x8000001E, 0, EBX, 15:8, threads_per_core, The number of threads per core is threads_per_core + 1
0388 # ECX: Node Identifiers
0389 0x8000001E, 0, ECX, 7:0, node_id, Node ID
0390 0x8000001E, 0, ECX, 10:8, nodes_per_processor, Nodes per processor { 0: 1 node, else reserved }
0391
0392 # 8000001F: AMD Secure Encryption
0393 0x8000001F, 0, EAX, 0, sme, Secure Memory Encryption
0394 0x8000001F, 0, EAX, 1, sev, Secure Encrypted Virtualization
0395 0x8000001F, 0, EAX, 2, vmpgflush, VM Page Flush MSR
0396 0x8000001F, 0, EAX, 3, seves, SEV Encrypted State
0397 0x8000001F, 0, EBX, 5:0, c-bit, Page table bit number used to enable memory encryption
0398 0x8000001F, 0, EBX, 11:6, mem_encrypt_physaddr_width, Reduction of physical address space in bits with SME enabled
0399 0x8000001F, 0, ECX, 31:0, num_encrypted_guests, Maximum ASID value that may be used for an SEV-enabled guest
0400 0x8000001F, 0, EDX, 31:0, minimum_sev_asid, Minimum ASID value that must be used for an SEV-enabled, SEV-ES-disabled guest
