0001
0002 #ifndef _ASM_X86_PERF_REGS_H
0003 #define _ASM_X86_PERF_REGS_H
0004
0005 enum perf_event_x86_regs {
0006 PERF_REG_X86_AX,
0007 PERF_REG_X86_BX,
0008 PERF_REG_X86_CX,
0009 PERF_REG_X86_DX,
0010 PERF_REG_X86_SI,
0011 PERF_REG_X86_DI,
0012 PERF_REG_X86_BP,
0013 PERF_REG_X86_SP,
0014 PERF_REG_X86_IP,
0015 PERF_REG_X86_FLAGS,
0016 PERF_REG_X86_CS,
0017 PERF_REG_X86_SS,
0018 PERF_REG_X86_DS,
0019 PERF_REG_X86_ES,
0020 PERF_REG_X86_FS,
0021 PERF_REG_X86_GS,
0022 PERF_REG_X86_R8,
0023 PERF_REG_X86_R9,
0024 PERF_REG_X86_R10,
0025 PERF_REG_X86_R11,
0026 PERF_REG_X86_R12,
0027 PERF_REG_X86_R13,
0028 PERF_REG_X86_R14,
0029 PERF_REG_X86_R15,
0030
0031 PERF_REG_X86_32_MAX = PERF_REG_X86_GS + 1,
0032 PERF_REG_X86_64_MAX = PERF_REG_X86_R15 + 1,
0033
0034
0035 PERF_REG_X86_XMM0 = 32,
0036 PERF_REG_X86_XMM1 = 34,
0037 PERF_REG_X86_XMM2 = 36,
0038 PERF_REG_X86_XMM3 = 38,
0039 PERF_REG_X86_XMM4 = 40,
0040 PERF_REG_X86_XMM5 = 42,
0041 PERF_REG_X86_XMM6 = 44,
0042 PERF_REG_X86_XMM7 = 46,
0043 PERF_REG_X86_XMM8 = 48,
0044 PERF_REG_X86_XMM9 = 50,
0045 PERF_REG_X86_XMM10 = 52,
0046 PERF_REG_X86_XMM11 = 54,
0047 PERF_REG_X86_XMM12 = 56,
0048 PERF_REG_X86_XMM13 = 58,
0049 PERF_REG_X86_XMM14 = 60,
0050 PERF_REG_X86_XMM15 = 62,
0051
0052
0053 PERF_REG_X86_XMM_MAX = PERF_REG_X86_XMM15 + 2,
0054 };
0055
0056 #define PERF_REG_EXTENDED_MASK (~((1ULL << PERF_REG_X86_XMM0) - 1))
0057
0058 #endif