0001
0002 #ifndef _ASM_X86_KVM_H
0003 #define _ASM_X86_KVM_H
0004
0005
0006
0007
0008
0009
0010 #include <linux/types.h>
0011 #include <linux/ioctl.h>
0012
0013 #define KVM_PIO_PAGE_OFFSET 1
0014 #define KVM_COALESCED_MMIO_PAGE_OFFSET 2
0015 #define KVM_DIRTY_LOG_PAGE_OFFSET 64
0016
0017 #define DE_VECTOR 0
0018 #define DB_VECTOR 1
0019 #define BP_VECTOR 3
0020 #define OF_VECTOR 4
0021 #define BR_VECTOR 5
0022 #define UD_VECTOR 6
0023 #define NM_VECTOR 7
0024 #define DF_VECTOR 8
0025 #define TS_VECTOR 10
0026 #define NP_VECTOR 11
0027 #define SS_VECTOR 12
0028 #define GP_VECTOR 13
0029 #define PF_VECTOR 14
0030 #define MF_VECTOR 16
0031 #define AC_VECTOR 17
0032 #define MC_VECTOR 18
0033 #define XM_VECTOR 19
0034 #define VE_VECTOR 20
0035
0036
0037 #define __KVM_HAVE_PIT
0038 #define __KVM_HAVE_IOAPIC
0039 #define __KVM_HAVE_IRQ_LINE
0040 #define __KVM_HAVE_MSI
0041 #define __KVM_HAVE_USER_NMI
0042 #define __KVM_HAVE_GUEST_DEBUG
0043 #define __KVM_HAVE_MSIX
0044 #define __KVM_HAVE_MCE
0045 #define __KVM_HAVE_PIT_STATE2
0046 #define __KVM_HAVE_XEN_HVM
0047 #define __KVM_HAVE_VCPU_EVENTS
0048 #define __KVM_HAVE_DEBUGREGS
0049 #define __KVM_HAVE_XSAVE
0050 #define __KVM_HAVE_XCRS
0051 #define __KVM_HAVE_READONLY_MEM
0052
0053
0054 #define KVM_NR_INTERRUPTS 256
0055
0056 struct kvm_memory_alias {
0057 __u32 slot;
0058 __u32 flags;
0059 __u64 guest_phys_addr;
0060 __u64 memory_size;
0061 __u64 target_phys_addr;
0062 };
0063
0064
0065 struct kvm_pic_state {
0066 __u8 last_irr;
0067 __u8 irr;
0068 __u8 imr;
0069 __u8 isr;
0070 __u8 priority_add;
0071 __u8 irq_base;
0072 __u8 read_reg_select;
0073 __u8 poll;
0074 __u8 special_mask;
0075 __u8 init_state;
0076 __u8 auto_eoi;
0077 __u8 rotate_on_auto_eoi;
0078 __u8 special_fully_nested_mode;
0079 __u8 init4;
0080 __u8 elcr;
0081 __u8 elcr_mask;
0082 };
0083
0084 #define KVM_IOAPIC_NUM_PINS 24
0085 struct kvm_ioapic_state {
0086 __u64 base_address;
0087 __u32 ioregsel;
0088 __u32 id;
0089 __u32 irr;
0090 __u32 pad;
0091 union {
0092 __u64 bits;
0093 struct {
0094 __u8 vector;
0095 __u8 delivery_mode:3;
0096 __u8 dest_mode:1;
0097 __u8 delivery_status:1;
0098 __u8 polarity:1;
0099 __u8 remote_irr:1;
0100 __u8 trig_mode:1;
0101 __u8 mask:1;
0102 __u8 reserve:7;
0103 __u8 reserved[4];
0104 __u8 dest_id;
0105 } fields;
0106 } redirtbl[KVM_IOAPIC_NUM_PINS];
0107 };
0108
0109 #define KVM_IRQCHIP_PIC_MASTER 0
0110 #define KVM_IRQCHIP_PIC_SLAVE 1
0111 #define KVM_IRQCHIP_IOAPIC 2
0112 #define KVM_NR_IRQCHIPS 3
0113
0114 #define KVM_RUN_X86_SMM (1 << 0)
0115 #define KVM_RUN_X86_BUS_LOCK (1 << 1)
0116
0117
0118 struct kvm_regs {
0119
0120 __u64 rax, rbx, rcx, rdx;
0121 __u64 rsi, rdi, rsp, rbp;
0122 __u64 r8, r9, r10, r11;
0123 __u64 r12, r13, r14, r15;
0124 __u64 rip, rflags;
0125 };
0126
0127
0128 #define KVM_APIC_REG_SIZE 0x400
0129 struct kvm_lapic_state {
0130 char regs[KVM_APIC_REG_SIZE];
0131 };
0132
0133 struct kvm_segment {
0134 __u64 base;
0135 __u32 limit;
0136 __u16 selector;
0137 __u8 type;
0138 __u8 present, dpl, db, s, l, g, avl;
0139 __u8 unusable;
0140 __u8 padding;
0141 };
0142
0143 struct kvm_dtable {
0144 __u64 base;
0145 __u16 limit;
0146 __u16 padding[3];
0147 };
0148
0149
0150
0151 struct kvm_sregs {
0152
0153 struct kvm_segment cs, ds, es, fs, gs, ss;
0154 struct kvm_segment tr, ldt;
0155 struct kvm_dtable gdt, idt;
0156 __u64 cr0, cr2, cr3, cr4, cr8;
0157 __u64 efer;
0158 __u64 apic_base;
0159 __u64 interrupt_bitmap[(KVM_NR_INTERRUPTS + 63) / 64];
0160 };
0161
0162 struct kvm_sregs2 {
0163
0164 struct kvm_segment cs, ds, es, fs, gs, ss;
0165 struct kvm_segment tr, ldt;
0166 struct kvm_dtable gdt, idt;
0167 __u64 cr0, cr2, cr3, cr4, cr8;
0168 __u64 efer;
0169 __u64 apic_base;
0170 __u64 flags;
0171 __u64 pdptrs[4];
0172 };
0173 #define KVM_SREGS2_FLAGS_PDPTRS_VALID 1
0174
0175
0176 struct kvm_fpu {
0177 __u8 fpr[8][16];
0178 __u16 fcw;
0179 __u16 fsw;
0180 __u8 ftwx;
0181 __u8 pad1;
0182 __u16 last_opcode;
0183 __u64 last_ip;
0184 __u64 last_dp;
0185 __u8 xmm[16][16];
0186 __u32 mxcsr;
0187 __u32 pad2;
0188 };
0189
0190 struct kvm_msr_entry {
0191 __u32 index;
0192 __u32 reserved;
0193 __u64 data;
0194 };
0195
0196
0197 struct kvm_msrs {
0198 __u32 nmsrs;
0199 __u32 pad;
0200
0201 struct kvm_msr_entry entries[];
0202 };
0203
0204
0205 struct kvm_msr_list {
0206 __u32 nmsrs;
0207 __u32 indices[];
0208 };
0209
0210
0211 #define KVM_MSR_FILTER_MAX_BITMAP_SIZE 0x600
0212
0213
0214 struct kvm_msr_filter_range {
0215 #define KVM_MSR_FILTER_READ (1 << 0)
0216 #define KVM_MSR_FILTER_WRITE (1 << 1)
0217 __u32 flags;
0218 __u32 nmsrs;
0219 __u32 base;
0220 __u8 *bitmap;
0221 };
0222
0223 #define KVM_MSR_FILTER_MAX_RANGES 16
0224 struct kvm_msr_filter {
0225 #define KVM_MSR_FILTER_DEFAULT_ALLOW (0 << 0)
0226 #define KVM_MSR_FILTER_DEFAULT_DENY (1 << 0)
0227 __u32 flags;
0228 struct kvm_msr_filter_range ranges[KVM_MSR_FILTER_MAX_RANGES];
0229 };
0230
0231 struct kvm_cpuid_entry {
0232 __u32 function;
0233 __u32 eax;
0234 __u32 ebx;
0235 __u32 ecx;
0236 __u32 edx;
0237 __u32 padding;
0238 };
0239
0240
0241 struct kvm_cpuid {
0242 __u32 nent;
0243 __u32 padding;
0244 struct kvm_cpuid_entry entries[];
0245 };
0246
0247 struct kvm_cpuid_entry2 {
0248 __u32 function;
0249 __u32 index;
0250 __u32 flags;
0251 __u32 eax;
0252 __u32 ebx;
0253 __u32 ecx;
0254 __u32 edx;
0255 __u32 padding[3];
0256 };
0257
0258 #define KVM_CPUID_FLAG_SIGNIFCANT_INDEX (1 << 0)
0259 #define KVM_CPUID_FLAG_STATEFUL_FUNC (1 << 1)
0260 #define KVM_CPUID_FLAG_STATE_READ_NEXT (1 << 2)
0261
0262
0263 struct kvm_cpuid2 {
0264 __u32 nent;
0265 __u32 padding;
0266 struct kvm_cpuid_entry2 entries[];
0267 };
0268
0269
0270 struct kvm_pit_channel_state {
0271 __u32 count;
0272 __u16 latched_count;
0273 __u8 count_latched;
0274 __u8 status_latched;
0275 __u8 status;
0276 __u8 read_state;
0277 __u8 write_state;
0278 __u8 write_latch;
0279 __u8 rw_mode;
0280 __u8 mode;
0281 __u8 bcd;
0282 __u8 gate;
0283 __s64 count_load_time;
0284 };
0285
0286 struct kvm_debug_exit_arch {
0287 __u32 exception;
0288 __u32 pad;
0289 __u64 pc;
0290 __u64 dr6;
0291 __u64 dr7;
0292 };
0293
0294 #define KVM_GUESTDBG_USE_SW_BP 0x00010000
0295 #define KVM_GUESTDBG_USE_HW_BP 0x00020000
0296 #define KVM_GUESTDBG_INJECT_DB 0x00040000
0297 #define KVM_GUESTDBG_INJECT_BP 0x00080000
0298 #define KVM_GUESTDBG_BLOCKIRQ 0x00100000
0299
0300
0301 struct kvm_guest_debug_arch {
0302 __u64 debugreg[8];
0303 };
0304
0305 struct kvm_pit_state {
0306 struct kvm_pit_channel_state channels[3];
0307 };
0308
0309 #define KVM_PIT_FLAGS_HPET_LEGACY 0x00000001
0310 #define KVM_PIT_FLAGS_SPEAKER_DATA_ON 0x00000002
0311
0312 struct kvm_pit_state2 {
0313 struct kvm_pit_channel_state channels[3];
0314 __u32 flags;
0315 __u32 reserved[9];
0316 };
0317
0318 struct kvm_reinject_control {
0319 __u8 pit_reinject;
0320 __u8 reserved[31];
0321 };
0322
0323
0324 #define KVM_VCPUEVENT_VALID_NMI_PENDING 0x00000001
0325 #define KVM_VCPUEVENT_VALID_SIPI_VECTOR 0x00000002
0326 #define KVM_VCPUEVENT_VALID_SHADOW 0x00000004
0327 #define KVM_VCPUEVENT_VALID_SMM 0x00000008
0328 #define KVM_VCPUEVENT_VALID_PAYLOAD 0x00000010
0329 #define KVM_VCPUEVENT_VALID_TRIPLE_FAULT 0x00000020
0330
0331
0332 #define KVM_X86_SHADOW_INT_MOV_SS 0x01
0333 #define KVM_X86_SHADOW_INT_STI 0x02
0334
0335
0336 struct kvm_vcpu_events {
0337 struct {
0338 __u8 injected;
0339 __u8 nr;
0340 __u8 has_error_code;
0341 __u8 pending;
0342 __u32 error_code;
0343 } exception;
0344 struct {
0345 __u8 injected;
0346 __u8 nr;
0347 __u8 soft;
0348 __u8 shadow;
0349 } interrupt;
0350 struct {
0351 __u8 injected;
0352 __u8 pending;
0353 __u8 masked;
0354 __u8 pad;
0355 } nmi;
0356 __u32 sipi_vector;
0357 __u32 flags;
0358 struct {
0359 __u8 smm;
0360 __u8 pending;
0361 __u8 smm_inside_nmi;
0362 __u8 latched_init;
0363 } smi;
0364 struct {
0365 __u8 pending;
0366 } triple_fault;
0367 __u8 reserved[26];
0368 __u8 exception_has_payload;
0369 __u64 exception_payload;
0370 };
0371
0372
0373 struct kvm_debugregs {
0374 __u64 db[4];
0375 __u64 dr6;
0376 __u64 dr7;
0377 __u64 flags;
0378 __u64 reserved[9];
0379 };
0380
0381
0382 struct kvm_xsave {
0383
0384
0385
0386
0387
0388
0389
0390
0391
0392
0393
0394
0395
0396 __u32 region[1024];
0397 __u32 extra[];
0398 };
0399
0400 #define KVM_MAX_XCRS 16
0401
0402 struct kvm_xcr {
0403 __u32 xcr;
0404 __u32 reserved;
0405 __u64 value;
0406 };
0407
0408 struct kvm_xcrs {
0409 __u32 nr_xcrs;
0410 __u32 flags;
0411 struct kvm_xcr xcrs[KVM_MAX_XCRS];
0412 __u64 padding[16];
0413 };
0414
0415 #define KVM_SYNC_X86_REGS (1UL << 0)
0416 #define KVM_SYNC_X86_SREGS (1UL << 1)
0417 #define KVM_SYNC_X86_EVENTS (1UL << 2)
0418
0419 #define KVM_SYNC_X86_VALID_FIELDS \
0420 (KVM_SYNC_X86_REGS| \
0421 KVM_SYNC_X86_SREGS| \
0422 KVM_SYNC_X86_EVENTS)
0423
0424
0425 struct kvm_sync_regs {
0426
0427
0428
0429
0430
0431 struct kvm_regs regs;
0432 struct kvm_sregs sregs;
0433 struct kvm_vcpu_events events;
0434 };
0435
0436 #define KVM_X86_QUIRK_LINT0_REENABLED (1 << 0)
0437 #define KVM_X86_QUIRK_CD_NW_CLEARED (1 << 1)
0438 #define KVM_X86_QUIRK_LAPIC_MMIO_HOLE (1 << 2)
0439 #define KVM_X86_QUIRK_OUT_7E_INC_RIP (1 << 3)
0440 #define KVM_X86_QUIRK_MISC_ENABLE_NO_MWAIT (1 << 4)
0441 #define KVM_X86_QUIRK_FIX_HYPERCALL_INSN (1 << 5)
0442 #define KVM_X86_QUIRK_MWAIT_NEVER_UD_FAULTS (1 << 6)
0443
0444 #define KVM_STATE_NESTED_FORMAT_VMX 0
0445 #define KVM_STATE_NESTED_FORMAT_SVM 1
0446
0447 #define KVM_STATE_NESTED_GUEST_MODE 0x00000001
0448 #define KVM_STATE_NESTED_RUN_PENDING 0x00000002
0449 #define KVM_STATE_NESTED_EVMCS 0x00000004
0450 #define KVM_STATE_NESTED_MTF_PENDING 0x00000008
0451 #define KVM_STATE_NESTED_GIF_SET 0x00000100
0452
0453 #define KVM_STATE_NESTED_SMM_GUEST_MODE 0x00000001
0454 #define KVM_STATE_NESTED_SMM_VMXON 0x00000002
0455
0456 #define KVM_STATE_NESTED_VMX_VMCS_SIZE 0x1000
0457
0458 #define KVM_STATE_NESTED_SVM_VMCB_SIZE 0x1000
0459
0460 #define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001
0461
0462
0463 #define KVM_X86_XCOMP_GUEST_SUPP 0
0464
0465 struct kvm_vmx_nested_state_data {
0466 __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
0467 __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE];
0468 };
0469
0470 struct kvm_vmx_nested_state_hdr {
0471 __u64 vmxon_pa;
0472 __u64 vmcs12_pa;
0473
0474 struct {
0475 __u16 flags;
0476 } smm;
0477
0478 __u16 pad;
0479
0480 __u32 flags;
0481 __u64 preemption_timer_deadline;
0482 };
0483
0484 struct kvm_svm_nested_state_data {
0485
0486 __u8 vmcb12[KVM_STATE_NESTED_SVM_VMCB_SIZE];
0487 };
0488
0489 struct kvm_svm_nested_state_hdr {
0490 __u64 vmcb_pa;
0491 };
0492
0493
0494 struct kvm_nested_state {
0495 __u16 flags;
0496 __u16 format;
0497 __u32 size;
0498
0499 union {
0500 struct kvm_vmx_nested_state_hdr vmx;
0501 struct kvm_svm_nested_state_hdr svm;
0502
0503
0504 __u8 pad[120];
0505 } hdr;
0506
0507
0508
0509
0510
0511
0512 union {
0513 struct kvm_vmx_nested_state_data vmx[0];
0514 struct kvm_svm_nested_state_data svm[0];
0515 } data;
0516 };
0517
0518
0519 struct kvm_pmu_event_filter {
0520 __u32 action;
0521 __u32 nevents;
0522 __u32 fixed_counter_bitmap;
0523 __u32 flags;
0524 __u32 pad[4];
0525 __u64 events[];
0526 };
0527
0528 #define KVM_PMU_EVENT_ALLOW 0
0529 #define KVM_PMU_EVENT_DENY 1
0530
0531
0532 #define KVM_VCPU_TSC_CTRL 0
0533 #define KVM_VCPU_TSC_OFFSET 0
0534
0535 #endif