include/asm/cpufeatures.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef _ASM_X86_CPUFEATURES_H
0003 #define _ASM_X86_CPUFEATURES_H
0004
0005 #ifndef _ASM_X86_REQUIRED_FEATURES_H
0006 #include <asm/required-features.h>
0007 #endif
0008
0009 #ifndef _ASM_X86_DISABLED_FEATURES_H
0010 #include <asm/disabled-features.h>
0011 #endif
0012
0013 /*
0014  * Defines x86 CPU feature bits
0015  */
0016 #define NCAPINTS            20     /* N 32-bit words worth of info */
0017 #define NBUGINTS            1      /* N 32-bit bug flags */
0018
0019 /*
0020  * Note: If the comment begins with a quoted string, that string is used
0021  * in /proc/cpuinfo instead of the macro name.  If the string is "",
0022  * this feature bit is not displayed in /proc/cpuinfo at all.
0023  *
0024  * When adding new features here that depend on other features,
0025  * please update the table in kernel/cpu/cpuid-deps.c as well.
0026  */
0027
0028 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
0029 #define X86_FEATURE_FPU         ( 0*32+ 0) /* Onboard FPU */
0030 #define X86_FEATURE_VME         ( 0*32+ 1) /* Virtual Mode Extensions */
0031 #define X86_FEATURE_DE          ( 0*32+ 2) /* Debugging Extensions */
0032 #define X86_FEATURE_PSE         ( 0*32+ 3) /* Page Size Extensions */
0033 #define X86_FEATURE_TSC         ( 0*32+ 4) /* Time Stamp Counter */
0034 #define X86_FEATURE_MSR         ( 0*32+ 5) /* Model-Specific Registers */
0035 #define X86_FEATURE_PAE         ( 0*32+ 6) /* Physical Address Extensions */
0036 #define X86_FEATURE_MCE         ( 0*32+ 7) /* Machine Check Exception */
0037 #define X86_FEATURE_CX8         ( 0*32+ 8) /* CMPXCHG8 instruction */
0038 #define X86_FEATURE_APIC        ( 0*32+ 9) /* Onboard APIC */
0039 #define X86_FEATURE_SEP         ( 0*32+11) /* SYSENTER/SYSEXIT */
0040 #define X86_FEATURE_MTRR        ( 0*32+12) /* Memory Type Range Registers */
0041 #define X86_FEATURE_PGE         ( 0*32+13) /* Page Global Enable */
0042 #define X86_FEATURE_MCA         ( 0*32+14) /* Machine Check Architecture */
0043 #define X86_FEATURE_CMOV        ( 0*32+15) /* CMOV instructions (plus FCMOVcc, FCOMI with FPU) */
0044 #define X86_FEATURE_PAT         ( 0*32+16) /* Page Attribute Table */
0045 #define X86_FEATURE_PSE36       ( 0*32+17) /* 36-bit PSEs */
0046 #define X86_FEATURE_PN          ( 0*32+18) /* Processor serial number */
0047 #define X86_FEATURE_CLFLUSH     ( 0*32+19) /* CLFLUSH instruction */
0048 #define X86_FEATURE_DS          ( 0*32+21) /* "dts" Debug Store */
0049 #define X86_FEATURE_ACPI        ( 0*32+22) /* ACPI via MSR */
0050 #define X86_FEATURE_MMX         ( 0*32+23) /* Multimedia Extensions */
0051 #define X86_FEATURE_FXSR        ( 0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
0052 #define X86_FEATURE_XMM         ( 0*32+25) /* "sse" */
0053 #define X86_FEATURE_XMM2        ( 0*32+26) /* "sse2" */
0054 #define X86_FEATURE_SELFSNOOP       ( 0*32+27) /* "ss" CPU self snoop */
0055 #define X86_FEATURE_HT          ( 0*32+28) /* Hyper-Threading */
0056 #define X86_FEATURE_ACC         ( 0*32+29) /* "tm" Automatic clock control */
0057 #define X86_FEATURE_IA64        ( 0*32+30) /* IA-64 processor */
0058 #define X86_FEATURE_PBE         ( 0*32+31) /* Pending Break Enable */
0059
0060 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
0061 /* Don't duplicate feature flags which are redundant with Intel! */
0062 #define X86_FEATURE_SYSCALL     ( 1*32+11) /* SYSCALL/SYSRET */
0063 #define X86_FEATURE_MP          ( 1*32+19) /* MP Capable */
0064 #define X86_FEATURE_NX          ( 1*32+20) /* Execute Disable */
0065 #define X86_FEATURE_MMXEXT      ( 1*32+22) /* AMD MMX extensions */
0066 #define X86_FEATURE_FXSR_OPT        ( 1*32+25) /* FXSAVE/FXRSTOR optimizations */
0067 #define X86_FEATURE_GBPAGES     ( 1*32+26) /* "pdpe1gb" GB pages */
0068 #define X86_FEATURE_RDTSCP      ( 1*32+27) /* RDTSCP */
0069 #define X86_FEATURE_LM          ( 1*32+29) /* Long Mode (x86-64, 64-bit support) */
0070 #define X86_FEATURE_3DNOWEXT        ( 1*32+30) /* AMD 3DNow extensions */
0071 #define X86_FEATURE_3DNOW       ( 1*32+31) /* 3DNow */
0072
0073 /* Transmeta-defined CPU features, CPUID level 0x80860001, word 2 */
0074 #define X86_FEATURE_RECOVERY        ( 2*32+ 0) /* CPU in recovery mode */
0075 #define X86_FEATURE_LONGRUN     ( 2*32+ 1) /* Longrun power control */
0076 #define X86_FEATURE_LRTI        ( 2*32+ 3) /* LongRun table interface */
0077
0078 /* Other features, Linux-defined mapping, word 3 */
0079 /* This range is used for feature bits which conflict or are synthesized */
0080 #define X86_FEATURE_CXMMX       ( 3*32+ 0) /* Cyrix MMX extensions */
0081 #define X86_FEATURE_K6_MTRR     ( 3*32+ 1) /* AMD K6 nonstandard MTRRs */
0082 #define X86_FEATURE_CYRIX_ARR       ( 3*32+ 2) /* Cyrix ARRs (= MTRRs) */
0083 #define X86_FEATURE_CENTAUR_MCR     ( 3*32+ 3) /* Centaur MCRs (= MTRRs) */
0084
0085 /* CPU types for specific tunings: */
0086 #define X86_FEATURE_K8          ( 3*32+ 4) /* "" Opteron, Athlon64 */
0087 /* FREE, was #define X86_FEATURE_K7         ( 3*32+ 5) "" Athlon */
0088 #define X86_FEATURE_P3          ( 3*32+ 6) /* "" P3 */
0089 #define X86_FEATURE_P4          ( 3*32+ 7) /* "" P4 */
0090 #define X86_FEATURE_CONSTANT_TSC    ( 3*32+ 8) /* TSC ticks at a constant rate */
0091 #define X86_FEATURE_UP          ( 3*32+ 9) /* SMP kernel running on UP */
0092 #define X86_FEATURE_ART         ( 3*32+10) /* Always running timer (ART) */
0093 #define X86_FEATURE_ARCH_PERFMON    ( 3*32+11) /* Intel Architectural PerfMon */
0094 #define X86_FEATURE_PEBS        ( 3*32+12) /* Precise-Event Based Sampling */
0095 #define X86_FEATURE_BTS         ( 3*32+13) /* Branch Trace Store */
0096 #define X86_FEATURE_SYSCALL32       ( 3*32+14) /* "" syscall in IA32 userspace */
0097 #define X86_FEATURE_SYSENTER32      ( 3*32+15) /* "" sysenter in IA32 userspace */
0098 #define X86_FEATURE_REP_GOOD        ( 3*32+16) /* REP microcode works well */
0099 /* FREE!                                ( 3*32+17) */
0100 #define X86_FEATURE_LFENCE_RDTSC    ( 3*32+18) /* "" LFENCE synchronizes RDTSC */
0101 #define X86_FEATURE_ACC_POWER       ( 3*32+19) /* AMD Accumulated Power Mechanism */
0102 #define X86_FEATURE_NOPL        ( 3*32+20) /* The NOPL (0F 1F) instructions */
0103 #define X86_FEATURE_ALWAYS      ( 3*32+21) /* "" Always-present feature */
0104 #define X86_FEATURE_XTOPOLOGY       ( 3*32+22) /* CPU topology enum extensions */
0105 #define X86_FEATURE_TSC_RELIABLE    ( 3*32+23) /* TSC is known to be reliable */
0106 #define X86_FEATURE_NONSTOP_TSC     ( 3*32+24) /* TSC does not stop in C states */
0107 #define X86_FEATURE_CPUID       ( 3*32+25) /* CPU has CPUID instruction itself */
0108 #define X86_FEATURE_EXTD_APICID     ( 3*32+26) /* Extended APICID (8 bits) */
0109 #define X86_FEATURE_AMD_DCM     ( 3*32+27) /* AMD multi-node processor */
0110 #define X86_FEATURE_APERFMPERF      ( 3*32+28) /* P-State hardware coordination feedback capability (APERF/MPERF MSRs) */
0111 #define X86_FEATURE_RAPL        ( 3*32+29) /* AMD/Hygon RAPL interface */
0112 #define X86_FEATURE_NONSTOP_TSC_S3  ( 3*32+30) /* TSC doesn't stop in S3 state */
0113 #define X86_FEATURE_TSC_KNOWN_FREQ  ( 3*32+31) /* TSC has known frequency */
0114
0115 /* Intel-defined CPU features, CPUID level 0x00000001 (ECX), word 4 */
0116 #define X86_FEATURE_XMM3        ( 4*32+ 0) /* "pni" SSE-3 */
0117 #define X86_FEATURE_PCLMULQDQ       ( 4*32+ 1) /* PCLMULQDQ instruction */
0118 #define X86_FEATURE_DTES64      ( 4*32+ 2) /* 64-bit Debug Store */
0119 #define X86_FEATURE_MWAIT       ( 4*32+ 3) /* "monitor" MONITOR/MWAIT support */
0120 #define X86_FEATURE_DSCPL       ( 4*32+ 4) /* "ds_cpl" CPL-qualified (filtered) Debug Store */
0121 #define X86_FEATURE_VMX         ( 4*32+ 5) /* Hardware virtualization */
0122 #define X86_FEATURE_SMX         ( 4*32+ 6) /* Safer Mode eXtensions */
0123 #define X86_FEATURE_EST         ( 4*32+ 7) /* Enhanced SpeedStep */
0124 #define X86_FEATURE_TM2         ( 4*32+ 8) /* Thermal Monitor 2 */
0125 #define X86_FEATURE_SSSE3       ( 4*32+ 9) /* Supplemental SSE-3 */
0126 #define X86_FEATURE_CID         ( 4*32+10) /* Context ID */
0127 #define X86_FEATURE_SDBG        ( 4*32+11) /* Silicon Debug */
0128 #define X86_FEATURE_FMA         ( 4*32+12) /* Fused multiply-add */
0129 #define X86_FEATURE_CX16        ( 4*32+13) /* CMPXCHG16B instruction */
0130 #define X86_FEATURE_XTPR        ( 4*32+14) /* Send Task Priority Messages */
0131 #define X86_FEATURE_PDCM        ( 4*32+15) /* Perf/Debug Capabilities MSR */
0132 #define X86_FEATURE_PCID        ( 4*32+17) /* Process Context Identifiers */
0133 #define X86_FEATURE_DCA         ( 4*32+18) /* Direct Cache Access */
0134 #define X86_FEATURE_XMM4_1      ( 4*32+19) /* "sse4_1" SSE-4.1 */
0135 #define X86_FEATURE_XMM4_2      ( 4*32+20) /* "sse4_2" SSE-4.2 */
0136 #define X86_FEATURE_X2APIC      ( 4*32+21) /* X2APIC */
0137 #define X86_FEATURE_MOVBE       ( 4*32+22) /* MOVBE instruction */
0138 #define X86_FEATURE_POPCNT      ( 4*32+23) /* POPCNT instruction */
0139 #define X86_FEATURE_TSC_DEADLINE_TIMER  ( 4*32+24) /* TSC deadline timer */
0140 #define X86_FEATURE_AES         ( 4*32+25) /* AES instructions */
0141 #define X86_FEATURE_XSAVE       ( 4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV instructions */
0142 #define X86_FEATURE_OSXSAVE     ( 4*32+27) /* "" XSAVE instruction enabled in the OS */
0143 #define X86_FEATURE_AVX         ( 4*32+28) /* Advanced Vector Extensions */
0144 #define X86_FEATURE_F16C        ( 4*32+29) /* 16-bit FP conversions */
0145 #define X86_FEATURE_RDRAND      ( 4*32+30) /* RDRAND instruction */
0146 #define X86_FEATURE_HYPERVISOR      ( 4*32+31) /* Running on a hypervisor */
0147
0148 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
0149 #define X86_FEATURE_XSTORE      ( 5*32+ 2) /* "rng" RNG present (xstore) */
0150 #define X86_FEATURE_XSTORE_EN       ( 5*32+ 3) /* "rng_en" RNG enabled */
0151 #define X86_FEATURE_XCRYPT      ( 5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
0152 #define X86_FEATURE_XCRYPT_EN       ( 5*32+ 7) /* "ace_en" on-CPU crypto enabled */
0153 #define X86_FEATURE_ACE2        ( 5*32+ 8) /* Advanced Cryptography Engine v2 */
0154 #define X86_FEATURE_ACE2_EN     ( 5*32+ 9) /* ACE v2 enabled */
0155 #define X86_FEATURE_PHE         ( 5*32+10) /* PadLock Hash Engine */
0156 #define X86_FEATURE_PHE_EN      ( 5*32+11) /* PHE enabled */
0157 #define X86_FEATURE_PMM         ( 5*32+12) /* PadLock Montgomery Multiplier */
0158 #define X86_FEATURE_PMM_EN      ( 5*32+13) /* PMM enabled */
0159
0160 /* More extended AMD flags: CPUID level 0x80000001, ECX, word 6 */
0161 #define X86_FEATURE_LAHF_LM     ( 6*32+ 0) /* LAHF/SAHF in long mode */
0162 #define X86_FEATURE_CMP_LEGACY      ( 6*32+ 1) /* If yes HyperThreading not valid */
0163 #define X86_FEATURE_SVM         ( 6*32+ 2) /* Secure Virtual Machine */
0164 #define X86_FEATURE_EXTAPIC     ( 6*32+ 3) /* Extended APIC space */
0165 #define X86_FEATURE_CR8_LEGACY      ( 6*32+ 4) /* CR8 in 32-bit mode */
0166 #define X86_FEATURE_ABM         ( 6*32+ 5) /* Advanced bit manipulation */
0167 #define X86_FEATURE_SSE4A       ( 6*32+ 6) /* SSE-4A */
0168 #define X86_FEATURE_MISALIGNSSE     ( 6*32+ 7) /* Misaligned SSE mode */
0169 #define X86_FEATURE_3DNOWPREFETCH   ( 6*32+ 8) /* 3DNow prefetch instructions */
0170 #define X86_FEATURE_OSVW        ( 6*32+ 9) /* OS Visible Workaround */
0171 #define X86_FEATURE_IBS         ( 6*32+10) /* Instruction Based Sampling */
0172 #define X86_FEATURE_XOP         ( 6*32+11) /* extended AVX instructions */
0173 #define X86_FEATURE_SKINIT      ( 6*32+12) /* SKINIT/STGI instructions */
0174 #define X86_FEATURE_WDT         ( 6*32+13) /* Watchdog timer */
0175 #define X86_FEATURE_LWP         ( 6*32+15) /* Light Weight Profiling */
0176 #define X86_FEATURE_FMA4        ( 6*32+16) /* 4 operands MAC instructions */
0177 #define X86_FEATURE_TCE         ( 6*32+17) /* Translation Cache Extension */
0178 #define X86_FEATURE_NODEID_MSR      ( 6*32+19) /* NodeId MSR */
0179 #define X86_FEATURE_TBM         ( 6*32+21) /* Trailing Bit Manipulations */
0180 #define X86_FEATURE_TOPOEXT     ( 6*32+22) /* Topology extensions CPUID leafs */
0181 #define X86_FEATURE_PERFCTR_CORE    ( 6*32+23) /* Core performance counter extensions */
0182 #define X86_FEATURE_PERFCTR_NB      ( 6*32+24) /* NB performance counter extensions */
0183 #define X86_FEATURE_BPEXT       ( 6*32+26) /* Data breakpoint extension */
0184 #define X86_FEATURE_PTSC        ( 6*32+27) /* Performance time-stamp counter */
0185 #define X86_FEATURE_PERFCTR_LLC     ( 6*32+28) /* Last Level Cache performance counter extensions */
0186 #define X86_FEATURE_MWAITX      ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX instructions) */
0187
0188 /*
0189  * Auxiliary flags: Linux defined - For features scattered in various
0190  * CPUID levels like 0x6, 0xA etc, word 7.
0191  *
0192  * Reuse free bits when adding new feature flags!
0193  */
0194 #define X86_FEATURE_RING3MWAIT      ( 7*32+ 0) /* Ring 3 MONITOR/MWAIT instructions */
0195 #define X86_FEATURE_CPUID_FAULT     ( 7*32+ 1) /* Intel CPUID faulting */
0196 #define X86_FEATURE_CPB         ( 7*32+ 2) /* AMD Core Performance Boost */
0197 #define X86_FEATURE_EPB         ( 7*32+ 3) /* IA32_ENERGY_PERF_BIAS support */
0198 #define X86_FEATURE_CAT_L3      ( 7*32+ 4) /* Cache Allocation Technology L3 */
0199 #define X86_FEATURE_CAT_L2      ( 7*32+ 5) /* Cache Allocation Technology L2 */
0200 #define X86_FEATURE_CDP_L3      ( 7*32+ 6) /* Code and Data Prioritization L3 */
0201 #define X86_FEATURE_INVPCID_SINGLE  ( 7*32+ 7) /* Effectively INVPCID && CR4.PCIDE=1 */
0202 #define X86_FEATURE_HW_PSTATE       ( 7*32+ 8) /* AMD HW-PState */
0203 #define X86_FEATURE_PROC_FEEDBACK   ( 7*32+ 9) /* AMD ProcFeedbackInterface */
0204 #define X86_FEATURE_XCOMPACTED      ( 7*32+10) /* "" Use compacted XSTATE (XSAVES or XSAVEC) */
0205 #define X86_FEATURE_PTI         ( 7*32+11) /* Kernel Page Table Isolation enabled */
0206 #define X86_FEATURE_KERNEL_IBRS     ( 7*32+12) /* "" Set/clear IBRS on kernel entry/exit */
0207 #define X86_FEATURE_RSB_VMEXIT      ( 7*32+13) /* "" Fill RSB on VM-Exit */
0208 #define X86_FEATURE_INTEL_PPIN      ( 7*32+14) /* Intel Processor Inventory Number */
0209 #define X86_FEATURE_CDP_L2      ( 7*32+15) /* Code and Data Prioritization L2 */
0210 #define X86_FEATURE_MSR_SPEC_CTRL   ( 7*32+16) /* "" MSR SPEC_CTRL is implemented */
0211 #define X86_FEATURE_SSBD        ( 7*32+17) /* Speculative Store Bypass Disable */
0212 #define X86_FEATURE_MBA         ( 7*32+18) /* Memory Bandwidth Allocation */
0213 #define X86_FEATURE_RSB_CTXSW       ( 7*32+19) /* "" Fill RSB on context switches */
0214 #define X86_FEATURE_PERFMON_V2      ( 7*32+20) /* AMD Performance Monitoring Version 2 */
0215 #define X86_FEATURE_USE_IBPB        ( 7*32+21) /* "" Indirect Branch Prediction Barrier enabled */
0216 #define X86_FEATURE_USE_IBRS_FW     ( 7*32+22) /* "" Use IBRS during runtime firmware calls */
0217 #define X86_FEATURE_SPEC_STORE_BYPASS_DISABLE   ( 7*32+23) /* "" Disable Speculative Store Bypass. */
0218 #define X86_FEATURE_LS_CFG_SSBD     ( 7*32+24)  /* "" AMD SSBD implementation via LS_CFG MSR */
0219 #define X86_FEATURE_IBRS        ( 7*32+25) /* Indirect Branch Restricted Speculation */
0220 #define X86_FEATURE_IBPB        ( 7*32+26) /* Indirect Branch Prediction Barrier */
0221 #define X86_FEATURE_STIBP       ( 7*32+27) /* Single Thread Indirect Branch Predictors */
0222 #define X86_FEATURE_ZEN         (7*32+28) /* "" CPU based on Zen microarchitecture */
0223 #define X86_FEATURE_L1TF_PTEINV     ( 7*32+29) /* "" L1TF workaround PTE inversion */
0224 #define X86_FEATURE_IBRS_ENHANCED   ( 7*32+30) /* Enhanced IBRS */
0225 #define X86_FEATURE_MSR_IA32_FEAT_CTL   ( 7*32+31) /* "" MSR IA32_FEAT_CTL configured */
0226
0227 /* Virtualization flags: Linux defined, word 8 */
0228 #define X86_FEATURE_TPR_SHADOW      ( 8*32+ 0) /* Intel TPR Shadow */
0229 #define X86_FEATURE_VNMI        ( 8*32+ 1) /* Intel Virtual NMI */
0230 #define X86_FEATURE_FLEXPRIORITY    ( 8*32+ 2) /* Intel FlexPriority */
0231 #define X86_FEATURE_EPT         ( 8*32+ 3) /* Intel Extended Page Table */
0232 #define X86_FEATURE_VPID        ( 8*32+ 4) /* Intel Virtual Processor ID */
0233
0234 #define X86_FEATURE_VMMCALL     ( 8*32+15) /* Prefer VMMCALL to VMCALL */
0235 #define X86_FEATURE_XENPV       ( 8*32+16) /* "" Xen paravirtual guest */
0236 #define X86_FEATURE_EPT_AD      ( 8*32+17) /* Intel Extended Page Table access-dirty bit */
0237 #define X86_FEATURE_VMCALL      ( 8*32+18) /* "" Hypervisor supports the VMCALL instruction */
0238 #define X86_FEATURE_VMW_VMMCALL     ( 8*32+19) /* "" VMware prefers VMMCALL hypercall instruction */
0239 #define X86_FEATURE_PVUNLOCK        ( 8*32+20) /* "" PV unlock function */
0240 #define X86_FEATURE_VCPUPREEMPT     ( 8*32+21) /* "" PV vcpu_is_preempted function */
0241 #define X86_FEATURE_TDX_GUEST       ( 8*32+22) /* Intel Trust Domain Extensions Guest */
0242
0243 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EBX), word 9 */
0244 #define X86_FEATURE_FSGSBASE        ( 9*32+ 0) /* RDFSBASE, WRFSBASE, RDGSBASE, WRGSBASE instructions*/
0245 #define X86_FEATURE_TSC_ADJUST      ( 9*32+ 1) /* TSC adjustment MSR 0x3B */
0246 #define X86_FEATURE_SGX         ( 9*32+ 2) /* Software Guard Extensions */
0247 #define X86_FEATURE_BMI1        ( 9*32+ 3) /* 1st group bit manipulation extensions */
0248 #define X86_FEATURE_HLE         ( 9*32+ 4) /* Hardware Lock Elision */
0249 #define X86_FEATURE_AVX2        ( 9*32+ 5) /* AVX2 instructions */
0250 #define X86_FEATURE_FDP_EXCPTN_ONLY ( 9*32+ 6) /* "" FPU data pointer updated only on x87 exceptions */
0251 #define X86_FEATURE_SMEP        ( 9*32+ 7) /* Supervisor Mode Execution Protection */
0252 #define X86_FEATURE_BMI2        ( 9*32+ 8) /* 2nd group bit manipulation extensions */
0253 #define X86_FEATURE_ERMS        ( 9*32+ 9) /* Enhanced REP MOVSB/STOSB instructions */
0254 #define X86_FEATURE_INVPCID     ( 9*32+10) /* Invalidate Processor Context ID */
0255 #define X86_FEATURE_RTM         ( 9*32+11) /* Restricted Transactional Memory */
0256 #define X86_FEATURE_CQM         ( 9*32+12) /* Cache QoS Monitoring */
0257 #define X86_FEATURE_ZERO_FCS_FDS    ( 9*32+13) /* "" Zero out FPU CS and FPU DS */
0258 #define X86_FEATURE_MPX         ( 9*32+14) /* Memory Protection Extension */
0259 #define X86_FEATURE_RDT_A       ( 9*32+15) /* Resource Director Technology Allocation */
0260 #define X86_FEATURE_AVX512F     ( 9*32+16) /* AVX-512 Foundation */
0261 #define X86_FEATURE_AVX512DQ        ( 9*32+17) /* AVX-512 DQ (Double/Quad granular) Instructions */
0262 #define X86_FEATURE_RDSEED      ( 9*32+18) /* RDSEED instruction */
0263 #define X86_FEATURE_ADX         ( 9*32+19) /* ADCX and ADOX instructions */
0264 #define X86_FEATURE_SMAP        ( 9*32+20) /* Supervisor Mode Access Prevention */
0265 #define X86_FEATURE_AVX512IFMA      ( 9*32+21) /* AVX-512 Integer Fused Multiply-Add instructions */
0266 #define X86_FEATURE_CLFLUSHOPT      ( 9*32+23) /* CLFLUSHOPT instruction */
0267 #define X86_FEATURE_CLWB        ( 9*32+24) /* CLWB instruction */
0268 #define X86_FEATURE_INTEL_PT        ( 9*32+25) /* Intel Processor Trace */
0269 #define X86_FEATURE_AVX512PF        ( 9*32+26) /* AVX-512 Prefetch */
0270 #define X86_FEATURE_AVX512ER        ( 9*32+27) /* AVX-512 Exponential and Reciprocal */
0271 #define X86_FEATURE_AVX512CD        ( 9*32+28) /* AVX-512 Conflict Detection */
0272 #define X86_FEATURE_SHA_NI      ( 9*32+29) /* SHA1/SHA256 Instruction Extensions */
0273 #define X86_FEATURE_AVX512BW        ( 9*32+30) /* AVX-512 BW (Byte/Word granular) Instructions */
0274 #define X86_FEATURE_AVX512VL        ( 9*32+31) /* AVX-512 VL (128/256 Vector Length) Extensions */
0275
0276 /* Extended state features, CPUID level 0x0000000d:1 (EAX), word 10 */
0277 #define X86_FEATURE_XSAVEOPT        (10*32+ 0) /* XSAVEOPT instruction */
0278 #define X86_FEATURE_XSAVEC      (10*32+ 1) /* XSAVEC instruction */
0279 #define X86_FEATURE_XGETBV1     (10*32+ 2) /* XGETBV with ECX = 1 instruction */
0280 #define X86_FEATURE_XSAVES      (10*32+ 3) /* XSAVES/XRSTORS instructions */
0281 #define X86_FEATURE_XFD         (10*32+ 4) /* "" eXtended Feature Disabling */
0282
0283 /*
0284  * Extended auxiliary flags: Linux defined - for features scattered in various
0285  * CPUID levels like 0xf, etc.
0286  *
0287  * Reuse free bits when adding new feature flags!
0288  */
0289 #define X86_FEATURE_CQM_LLC     (11*32+ 0) /* LLC QoS if 1 */
0290 #define X86_FEATURE_CQM_OCCUP_LLC   (11*32+ 1) /* LLC occupancy monitoring */
0291 #define X86_FEATURE_CQM_MBM_TOTAL   (11*32+ 2) /* LLC Total MBM monitoring */
0292 #define X86_FEATURE_CQM_MBM_LOCAL   (11*32+ 3) /* LLC Local MBM monitoring */
0293 #define X86_FEATURE_FENCE_SWAPGS_USER   (11*32+ 4) /* "" LFENCE in user entry SWAPGS path */
0294 #define X86_FEATURE_FENCE_SWAPGS_KERNEL (11*32+ 5) /* "" LFENCE in kernel entry SWAPGS path */
0295 #define X86_FEATURE_SPLIT_LOCK_DETECT   (11*32+ 6) /* #AC for split lock */
0296 #define X86_FEATURE_PER_THREAD_MBA  (11*32+ 7) /* "" Per-thread Memory Bandwidth Allocation */
0297 #define X86_FEATURE_SGX1        (11*32+ 8) /* "" Basic SGX */
0298 #define X86_FEATURE_SGX2        (11*32+ 9) /* "" SGX Enclave Dynamic Memory Management (EDMM) */
0299 #define X86_FEATURE_ENTRY_IBPB      (11*32+10) /* "" Issue an IBPB on kernel entry */
0300 #define X86_FEATURE_RRSBA_CTRL      (11*32+11) /* "" RET prediction control */
0301 #define X86_FEATURE_RETPOLINE       (11*32+12) /* "" Generic Retpoline mitigation for Spectre variant 2 */
0302 #define X86_FEATURE_RETPOLINE_LFENCE    (11*32+13) /* "" Use LFENCE for Spectre variant 2 */
0303 #define X86_FEATURE_RETHUNK     (11*32+14) /* "" Use REturn THUNK */
0304 #define X86_FEATURE_UNRET       (11*32+15) /* "" AMD BTB untrain return */
0305 #define X86_FEATURE_USE_IBPB_FW     (11*32+16) /* "" Use IBPB during runtime firmware calls */
0306 #define X86_FEATURE_RSB_VMEXIT_LITE (11*32+17) /* "" Fill RSB on VM exit when EIBRS is enabled */
0307
0308 /* Intel-defined CPU features, CPUID level 0x00000007:1 (EAX), word 12 */
0309 #define X86_FEATURE_AVX_VNNI        (12*32+ 4) /* AVX VNNI instructions */
0310 #define X86_FEATURE_AVX512_BF16     (12*32+ 5) /* AVX512 BFLOAT16 instructions */
0311
0312 /* AMD-defined CPU features, CPUID level 0x80000008 (EBX), word 13 */
0313 #define X86_FEATURE_CLZERO      (13*32+ 0) /* CLZERO instruction */
0314 #define X86_FEATURE_IRPERF      (13*32+ 1) /* Instructions Retired Count */
0315 #define X86_FEATURE_XSAVEERPTR      (13*32+ 2) /* Always save/restore FP error pointers */
0316 #define X86_FEATURE_RDPRU       (13*32+ 4) /* Read processor register at user level */
0317 #define X86_FEATURE_WBNOINVD        (13*32+ 9) /* WBNOINVD instruction */
0318 #define X86_FEATURE_AMD_IBPB        (13*32+12) /* "" Indirect Branch Prediction Barrier */
0319 #define X86_FEATURE_AMD_IBRS        (13*32+14) /* "" Indirect Branch Restricted Speculation */
0320 #define X86_FEATURE_AMD_STIBP       (13*32+15) /* "" Single Thread Indirect Branch Predictors */
0321 #define X86_FEATURE_AMD_STIBP_ALWAYS_ON (13*32+17) /* "" Single Thread Indirect Branch Predictors always-on preferred */
0322 #define X86_FEATURE_AMD_PPIN        (13*32+23) /* Protected Processor Inventory Number */
0323 #define X86_FEATURE_AMD_SSBD        (13*32+24) /* "" Speculative Store Bypass Disable */
0324 #define X86_FEATURE_VIRT_SSBD       (13*32+25) /* Virtualized Speculative Store Bypass Disable */
0325 #define X86_FEATURE_AMD_SSB_NO      (13*32+26) /* "" Speculative Store Bypass is fixed in hardware. */
0326 #define X86_FEATURE_CPPC        (13*32+27) /* Collaborative Processor Performance Control */
0327 #define X86_FEATURE_BTC_NO      (13*32+29) /* "" Not vulnerable to Branch Type Confusion */
0328 #define X86_FEATURE_BRS         (13*32+31) /* Branch Sampling available */
0329
0330 /* Thermal and Power Management Leaf, CPUID level 0x00000006 (EAX), word 14 */
0331 #define X86_FEATURE_DTHERM      (14*32+ 0) /* Digital Thermal Sensor */
0332 #define X86_FEATURE_IDA         (14*32+ 1) /* Intel Dynamic Acceleration */
0333 #define X86_FEATURE_ARAT        (14*32+ 2) /* Always Running APIC Timer */
0334 #define X86_FEATURE_PLN         (14*32+ 4) /* Intel Power Limit Notification */
0335 #define X86_FEATURE_PTS         (14*32+ 6) /* Intel Package Thermal Status */
0336 #define X86_FEATURE_HWP         (14*32+ 7) /* Intel Hardware P-states */
0337 #define X86_FEATURE_HWP_NOTIFY      (14*32+ 8) /* HWP Notification */
0338 #define X86_FEATURE_HWP_ACT_WINDOW  (14*32+ 9) /* HWP Activity Window */
0339 #define X86_FEATURE_HWP_EPP     (14*32+10) /* HWP Energy Perf. Preference */
0340 #define X86_FEATURE_HWP_PKG_REQ     (14*32+11) /* HWP Package Level Request */
0341 #define X86_FEATURE_HFI         (14*32+19) /* Hardware Feedback Interface */
0342
0343 /* AMD SVM Feature Identification, CPUID level 0x8000000a (EDX), word 15 */
0344 #define X86_FEATURE_NPT         (15*32+ 0) /* Nested Page Table support */
0345 #define X86_FEATURE_LBRV        (15*32+ 1) /* LBR Virtualization support */
0346 #define X86_FEATURE_SVML        (15*32+ 2) /* "svm_lock" SVM locking MSR */
0347 #define X86_FEATURE_NRIPS       (15*32+ 3) /* "nrip_save" SVM next_rip save */
0348 #define X86_FEATURE_TSCRATEMSR      (15*32+ 4) /* "tsc_scale" TSC scaling support */
0349 #define X86_FEATURE_VMCBCLEAN       (15*32+ 5) /* "vmcb_clean" VMCB clean bits support */
0350 #define X86_FEATURE_FLUSHBYASID     (15*32+ 6) /* flush-by-ASID support */
0351 #define X86_FEATURE_DECODEASSISTS   (15*32+ 7) /* Decode Assists support */
0352 #define X86_FEATURE_PAUSEFILTER     (15*32+10) /* filtered pause intercept */
0353 #define X86_FEATURE_PFTHRESHOLD     (15*32+12) /* pause filter threshold */
0354 #define X86_FEATURE_AVIC        (15*32+13) /* Virtual Interrupt Controller */
0355 #define X86_FEATURE_V_VMSAVE_VMLOAD (15*32+15) /* Virtual VMSAVE VMLOAD */
0356 #define X86_FEATURE_VGIF        (15*32+16) /* Virtual GIF */
0357 #define X86_FEATURE_X2AVIC      (15*32+18) /* Virtual x2apic */
0358 #define X86_FEATURE_V_SPEC_CTRL     (15*32+20) /* Virtual SPEC_CTRL */
0359 #define X86_FEATURE_SVME_ADDR_CHK   (15*32+28) /* "" SVME addr check */
0360
0361 /* Intel-defined CPU features, CPUID level 0x00000007:0 (ECX), word 16 */
0362 #define X86_FEATURE_AVX512VBMI      (16*32+ 1) /* AVX512 Vector Bit Manipulation instructions*/
0363 #define X86_FEATURE_UMIP        (16*32+ 2) /* User Mode Instruction Protection */
0364 #define X86_FEATURE_PKU         (16*32+ 3) /* Protection Keys for Userspace */
0365 #define X86_FEATURE_OSPKE       (16*32+ 4) /* OS Protection Keys Enable */
0366 #define X86_FEATURE_WAITPKG     (16*32+ 5) /* UMONITOR/UMWAIT/TPAUSE Instructions */
0367 #define X86_FEATURE_AVX512_VBMI2    (16*32+ 6) /* Additional AVX512 Vector Bit Manipulation Instructions */
0368 #define X86_FEATURE_GFNI        (16*32+ 8) /* Galois Field New Instructions */
0369 #define X86_FEATURE_VAES        (16*32+ 9) /* Vector AES */
0370 #define X86_FEATURE_VPCLMULQDQ      (16*32+10) /* Carry-Less Multiplication Double Quadword */
0371 #define X86_FEATURE_AVX512_VNNI     (16*32+11) /* Vector Neural Network Instructions */
0372 #define X86_FEATURE_AVX512_BITALG   (16*32+12) /* Support for VPOPCNT[B,W] and VPSHUF-BITQMB instructions */
0373 #define X86_FEATURE_TME         (16*32+13) /* Intel Total Memory Encryption */
0374 #define X86_FEATURE_AVX512_VPOPCNTDQ    (16*32+14) /* POPCNT for vectors of DW/QW */
0375 #define X86_FEATURE_LA57        (16*32+16) /* 5-level page tables */
0376 #define X86_FEATURE_RDPID       (16*32+22) /* RDPID instruction */
0377 #define X86_FEATURE_BUS_LOCK_DETECT (16*32+24) /* Bus Lock detect */
0378 #define X86_FEATURE_CLDEMOTE        (16*32+25) /* CLDEMOTE instruction */
0379 #define X86_FEATURE_MOVDIRI     (16*32+27) /* MOVDIRI instruction */
0380 #define X86_FEATURE_MOVDIR64B       (16*32+28) /* MOVDIR64B instruction */
0381 #define X86_FEATURE_ENQCMD      (16*32+29) /* ENQCMD and ENQCMDS instructions */
0382 #define X86_FEATURE_SGX_LC      (16*32+30) /* Software Guard Extensions Launch Control */
0383
0384 /* AMD-defined CPU features, CPUID level 0x80000007 (EBX), word 17 */
0385 #define X86_FEATURE_OVERFLOW_RECOV  (17*32+ 0) /* MCA overflow recovery support */
0386 #define X86_FEATURE_SUCCOR      (17*32+ 1) /* Uncorrectable error containment and recovery */
0387 #define X86_FEATURE_SMCA        (17*32+ 3) /* Scalable MCA */
0388
0389 /* Intel-defined CPU features, CPUID level 0x00000007:0 (EDX), word 18 */
0390 #define X86_FEATURE_AVX512_4VNNIW   (18*32+ 2) /* AVX-512 Neural Network Instructions */
0391 #define X86_FEATURE_AVX512_4FMAPS   (18*32+ 3) /* AVX-512 Multiply Accumulation Single precision */
0392 #define X86_FEATURE_FSRM        (18*32+ 4) /* Fast Short Rep Mov */
0393 #define X86_FEATURE_AVX512_VP2INTERSECT (18*32+ 8) /* AVX-512 Intersect for D/Q */
0394 #define X86_FEATURE_SRBDS_CTRL      (18*32+ 9) /* "" SRBDS mitigation MSR available */
0395 #define X86_FEATURE_MD_CLEAR        (18*32+10) /* VERW clears CPU buffers */
0396 #define X86_FEATURE_RTM_ALWAYS_ABORT    (18*32+11) /* "" RTM transaction always aborts */
0397 #define X86_FEATURE_TSX_FORCE_ABORT (18*32+13) /* "" TSX_FORCE_ABORT */
0398 #define X86_FEATURE_SERIALIZE       (18*32+14) /* SERIALIZE instruction */
0399 #define X86_FEATURE_HYBRID_CPU      (18*32+15) /* "" This part has CPUs of more than one type */
0400 #define X86_FEATURE_TSXLDTRK        (18*32+16) /* TSX Suspend Load Address Tracking */
0401 #define X86_FEATURE_PCONFIG     (18*32+18) /* Intel PCONFIG */
0402 #define X86_FEATURE_ARCH_LBR        (18*32+19) /* Intel ARCH LBR */
0403 #define X86_FEATURE_IBT         (18*32+20) /* Indirect Branch Tracking */
0404 #define X86_FEATURE_AMX_BF16        (18*32+22) /* AMX bf16 Support */
0405 #define X86_FEATURE_AVX512_FP16     (18*32+23) /* AVX512 FP16 */
0406 #define X86_FEATURE_AMX_TILE        (18*32+24) /* AMX tile Support */
0407 #define X86_FEATURE_AMX_INT8        (18*32+25) /* AMX int8 Support */
0408 #define X86_FEATURE_SPEC_CTRL       (18*32+26) /* "" Speculation Control (IBRS + IBPB) */
0409 #define X86_FEATURE_INTEL_STIBP     (18*32+27) /* "" Single Thread Indirect Branch Predictors */
0410 #define X86_FEATURE_FLUSH_L1D       (18*32+28) /* Flush L1D cache */
0411 #define X86_FEATURE_ARCH_CAPABILITIES   (18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
0412 #define X86_FEATURE_CORE_CAPABILITIES   (18*32+30) /* "" IA32_CORE_CAPABILITIES MSR */
0413 #define X86_FEATURE_SPEC_CTRL_SSBD  (18*32+31) /* "" Speculative Store Bypass Disable */
0414
0415 /* AMD-defined memory encryption features, CPUID level 0x8000001f (EAX), word 19 */
0416 #define X86_FEATURE_SME         (19*32+ 0) /* AMD Secure Memory Encryption */
0417 #define X86_FEATURE_SEV         (19*32+ 1) /* AMD Secure Encrypted Virtualization */
0418 #define X86_FEATURE_VM_PAGE_FLUSH   (19*32+ 2) /* "" VM Page Flush MSR is supported */
0419 #define X86_FEATURE_SEV_ES      (19*32+ 3) /* AMD Secure Encrypted Virtualization - Encrypted State */
0420 #define X86_FEATURE_V_TSC_AUX       (19*32+ 9) /* "" Virtual TSC_AUX */
0421 #define X86_FEATURE_SME_COHERENT    (19*32+10) /* "" AMD hardware-enforced cache coherency */
0422
0423 /*
0424  * BUG word(s)
0425  */
0426 #define X86_BUG(x)          (NCAPINTS*32 + (x))
0427
0428 #define X86_BUG_F00F            X86_BUG(0) /* Intel F00F */
0429 #define X86_BUG_FDIV            X86_BUG(1) /* FPU FDIV */
0430 #define X86_BUG_COMA            X86_BUG(2) /* Cyrix 6x86 coma */
0431 #define X86_BUG_AMD_TLB_MMATCH      X86_BUG(3) /* "tlb_mmatch" AMD Erratum 383 */
0432 #define X86_BUG_AMD_APIC_C1E        X86_BUG(4) /* "apic_c1e" AMD Erratum 400 */
0433 #define X86_BUG_11AP            X86_BUG(5) /* Bad local APIC aka 11AP */
0434 #define X86_BUG_FXSAVE_LEAK     X86_BUG(6) /* FXSAVE leaks FOP/FIP/FOP */
0435 #define X86_BUG_CLFLUSH_MONITOR     X86_BUG(7) /* AAI65, CLFLUSH required before MONITOR */
0436 #define X86_BUG_SYSRET_SS_ATTRS     X86_BUG(8) /* SYSRET doesn't fix up SS attrs */
0437 #ifdef CONFIG_X86_32
0438 /*
0439  * 64-bit kernels don't use X86_BUG_ESPFIX.  Make the define conditional
0440  * to avoid confusion.
0441  */
0442 #define X86_BUG_ESPFIX          X86_BUG(9) /* "" IRET to 16-bit SS corrupts ESP/RSP high bits */
0443 #endif
0444 #define X86_BUG_NULL_SEG        X86_BUG(10) /* Nulling a selector preserves the base */
0445 #define X86_BUG_SWAPGS_FENCE        X86_BUG(11) /* SWAPGS without input dep on GS */
0446 #define X86_BUG_MONITOR         X86_BUG(12) /* IPI required to wake up remote CPU */
0447 #define X86_BUG_AMD_E400        X86_BUG(13) /* CPU is among the affected by Erratum 400 */
0448 #define X86_BUG_CPU_MELTDOWN        X86_BUG(14) /* CPU is affected by meltdown attack and needs kernel page table isolation */
0449 #define X86_BUG_SPECTRE_V1      X86_BUG(15) /* CPU is affected by Spectre variant 1 attack with conditional branches */
0450 #define X86_BUG_SPECTRE_V2      X86_BUG(16) /* CPU is affected by Spectre variant 2 attack with indirect branches */
0451 #define X86_BUG_SPEC_STORE_BYPASS   X86_BUG(17) /* CPU is affected by speculative store bypass attack */
0452 #define X86_BUG_L1TF            X86_BUG(18) /* CPU is affected by L1 Terminal Fault */
0453 #define X86_BUG_MDS         X86_BUG(19) /* CPU is affected by Microarchitectural data sampling */
0454 #define X86_BUG_MSBDS_ONLY      X86_BUG(20) /* CPU is only affected by the  MSDBS variant of BUG_MDS */
0455 #define X86_BUG_SWAPGS          X86_BUG(21) /* CPU is affected by speculation through SWAPGS */
0456 #define X86_BUG_TAA         X86_BUG(22) /* CPU is affected by TSX Async Abort(TAA) */
0457 #define X86_BUG_ITLB_MULTIHIT       X86_BUG(23) /* CPU may incur MCE during certain page attribute changes */
0458 #define X86_BUG_SRBDS           X86_BUG(24) /* CPU may leak RNG bits if not mitigated */
0459 #define X86_BUG_MMIO_STALE_DATA     X86_BUG(25) /* CPU is affected by Processor MMIO Stale Data vulnerabilities */
0460 #define X86_BUG_MMIO_UNKNOWN        X86_BUG(26) /* CPU is too old and its MMIO Stale Data status is unknown */
0461 #define X86_BUG_RETBLEED        X86_BUG(27) /* CPU is affected by RETBleed */
0462 #define X86_BUG_EIBRS_PBRSB     X86_BUG(28) /* EIBRS is vulnerable to Post Barrier RSB Predictions */
0463
0464 #endif /* _ASM_X86_CPUFEATURES_H */