include/asm/barrier.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copied from the kernel sources:
0004  *
0005  * Copyright (C) 1999, 2000  Niibe Yutaka  &  Kaz Kojima
0006  * Copyright (C) 2002 Paul Mundt
0007  */
0008 #ifndef __TOOLS_LINUX_ASM_SH_BARRIER_H
0009 #define __TOOLS_LINUX_ASM_SH_BARRIER_H
0010
0011 /*
0012  * A brief note on ctrl_barrier(), the control register write barrier.
0013  *
0014  * Legacy SH cores typically require a sequence of 8 nops after
0015  * modification of a control register in order for the changes to take
0016  * effect. On newer cores (like the sh4a and sh5) this is accomplished
0017  * with icbi.
0018  *
0019  * Also note that on sh4a in the icbi case we can forego a synco for the
0020  * write barrier, as it's not necessary for control registers.
0021  *
0022  * Historically we have only done this type of barrier for the MMUCR, but
0023  * it's also necessary for the CCR, so we make it generic here instead.
0024  */
0025 #if defined(__SH4A__)
0026 #define mb()        __asm__ __volatile__ ("synco": : :"memory")
0027 #define rmb()       mb()
0028 #define wmb()       mb()
0029 #endif
0030
0031 #include <asm-generic/barrier.h>
0032
0033 #endif /* __TOOLS_LINUX_ASM_SH_BARRIER_H */