0001
0002 #ifndef _ASM_S390_PERF_REGS_H
0003 #define _ASM_S390_PERF_REGS_H
0004
0005 enum perf_event_s390_regs {
0006 PERF_REG_S390_R0,
0007 PERF_REG_S390_R1,
0008 PERF_REG_S390_R2,
0009 PERF_REG_S390_R3,
0010 PERF_REG_S390_R4,
0011 PERF_REG_S390_R5,
0012 PERF_REG_S390_R6,
0013 PERF_REG_S390_R7,
0014 PERF_REG_S390_R8,
0015 PERF_REG_S390_R9,
0016 PERF_REG_S390_R10,
0017 PERF_REG_S390_R11,
0018 PERF_REG_S390_R12,
0019 PERF_REG_S390_R13,
0020 PERF_REG_S390_R14,
0021 PERF_REG_S390_R15,
0022 PERF_REG_S390_FP0,
0023 PERF_REG_S390_FP1,
0024 PERF_REG_S390_FP2,
0025 PERF_REG_S390_FP3,
0026 PERF_REG_S390_FP4,
0027 PERF_REG_S390_FP5,
0028 PERF_REG_S390_FP6,
0029 PERF_REG_S390_FP7,
0030 PERF_REG_S390_FP8,
0031 PERF_REG_S390_FP9,
0032 PERF_REG_S390_FP10,
0033 PERF_REG_S390_FP11,
0034 PERF_REG_S390_FP12,
0035 PERF_REG_S390_FP13,
0036 PERF_REG_S390_FP14,
0037 PERF_REG_S390_FP15,
0038 PERF_REG_S390_MASK,
0039 PERF_REG_S390_PC,
0040
0041 PERF_REG_S390_MAX
0042 };
0043
0044 #endif