include/asm/barrier.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copied from the kernel sources:
0004  *
0005  * Copyright IBM Corp. 1999, 2009
0006  *
0007  * Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
0008  */
0009
0010 #ifndef __TOOLS_LINUX_ASM_BARRIER_H
0011 #define __TOOLS_LINUX_ASM_BARRIER_H
0012
0013 /*
0014  * Force strict CPU ordering.
0015  * And yes, this is required on UP too when we're talking
0016  * to devices.
0017  */
0018
0019 #ifdef CONFIG_HAVE_MARCH_Z196_FEATURES
0020 /* Fast-BCR without checkpoint synchronization */
0021 #define __ASM_BARRIER "bcr 14,0\n"
0022 #else
0023 #define __ASM_BARRIER "bcr 15,0\n"
0024 #endif
0025
0026 #define mb() do {  asm volatile(__ASM_BARRIER : : : "memory"); } while (0)
0027
0028 #define rmb()               mb()
0029 #define wmb()               mb()
0030
0031 #define smp_store_release(p, v)         \
0032 do {                        \
0033     barrier();              \
0034     WRITE_ONCE(*p, v);          \
0035 } while (0)
0036
0037 #define smp_load_acquire(p)         \
0038 ({                      \
0039     typeof(*p) ___p1 = READ_ONCE(*p);   \
0040     barrier();              \
0041     ___p1;                  \
0042 })
0043
0044 #endif /* __TOOLS_LIB_ASM_BARRIER_H */