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0004 #ifndef _ASM_RISCV_PERF_REGS_H
0005 #define _ASM_RISCV_PERF_REGS_H
0006
0007 enum perf_event_riscv_regs {
0008 PERF_REG_RISCV_PC,
0009 PERF_REG_RISCV_RA,
0010 PERF_REG_RISCV_SP,
0011 PERF_REG_RISCV_GP,
0012 PERF_REG_RISCV_TP,
0013 PERF_REG_RISCV_T0,
0014 PERF_REG_RISCV_T1,
0015 PERF_REG_RISCV_T2,
0016 PERF_REG_RISCV_S0,
0017 PERF_REG_RISCV_S1,
0018 PERF_REG_RISCV_A0,
0019 PERF_REG_RISCV_A1,
0020 PERF_REG_RISCV_A2,
0021 PERF_REG_RISCV_A3,
0022 PERF_REG_RISCV_A4,
0023 PERF_REG_RISCV_A5,
0024 PERF_REG_RISCV_A6,
0025 PERF_REG_RISCV_A7,
0026 PERF_REG_RISCV_S2,
0027 PERF_REG_RISCV_S3,
0028 PERF_REG_RISCV_S4,
0029 PERF_REG_RISCV_S5,
0030 PERF_REG_RISCV_S6,
0031 PERF_REG_RISCV_S7,
0032 PERF_REG_RISCV_S8,
0033 PERF_REG_RISCV_S9,
0034 PERF_REG_RISCV_S10,
0035 PERF_REG_RISCV_S11,
0036 PERF_REG_RISCV_T3,
0037 PERF_REG_RISCV_T4,
0038 PERF_REG_RISCV_T5,
0039 PERF_REG_RISCV_T6,
0040 PERF_REG_RISCV_MAX,
0041 };
0042 #endif