0001
0002 #ifndef _ASM_MIPS_PERF_REGS_H
0003 #define _ASM_MIPS_PERF_REGS_H
0004
0005 enum perf_event_mips_regs {
0006 PERF_REG_MIPS_PC,
0007 PERF_REG_MIPS_R1,
0008 PERF_REG_MIPS_R2,
0009 PERF_REG_MIPS_R3,
0010 PERF_REG_MIPS_R4,
0011 PERF_REG_MIPS_R5,
0012 PERF_REG_MIPS_R6,
0013 PERF_REG_MIPS_R7,
0014 PERF_REG_MIPS_R8,
0015 PERF_REG_MIPS_R9,
0016 PERF_REG_MIPS_R10,
0017 PERF_REG_MIPS_R11,
0018 PERF_REG_MIPS_R12,
0019 PERF_REG_MIPS_R13,
0020 PERF_REG_MIPS_R14,
0021 PERF_REG_MIPS_R15,
0022 PERF_REG_MIPS_R16,
0023 PERF_REG_MIPS_R17,
0024 PERF_REG_MIPS_R18,
0025 PERF_REG_MIPS_R19,
0026 PERF_REG_MIPS_R20,
0027 PERF_REG_MIPS_R21,
0028 PERF_REG_MIPS_R22,
0029 PERF_REG_MIPS_R23,
0030 PERF_REG_MIPS_R24,
0031 PERF_REG_MIPS_R25,
0032 PERF_REG_MIPS_R26,
0033 PERF_REG_MIPS_R27,
0034 PERF_REG_MIPS_R28,
0035 PERF_REG_MIPS_R29,
0036 PERF_REG_MIPS_R30,
0037 PERF_REG_MIPS_R31,
0038 PERF_REG_MIPS_MAX = PERF_REG_MIPS_R31 + 1,
0039 };
0040 #endif