uapi/asm/kvm.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * This file is subject to the terms and conditions of the GNU General Public
0004  * License.  See the file "COPYING" in the main directory of this archive
0005  * for more details.
0006  *
0007  * Copyright (C) 2012  MIPS Technologies, Inc.  All rights reserved.
0008  * Copyright (C) 2013 Cavium, Inc.
0009  * Authors: Sanjay Lal <sanjayl@kymasys.com>
0010  */
0011
0012 #ifndef __LINUX_KVM_MIPS_H
0013 #define __LINUX_KVM_MIPS_H
0014
0015 #include <linux/types.h>
0016
0017 /*
0018  * KVM MIPS specific structures and definitions.
0019  *
0020  * Some parts derived from the x86 version of this file.
0021  */
0022
0023 /*
0024  * for KVM_GET_REGS and KVM_SET_REGS
0025  *
0026  * If Config[AT] is zero (32-bit CPU), the register contents are
0027  * stored in the lower 32-bits of the struct kvm_regs fields and sign
0028  * extended to 64-bits.
0029  */
0030 struct kvm_regs {
0031     /* out (KVM_GET_REGS) / in (KVM_SET_REGS) */
0032     __u64 gpr[32];
0033     __u64 hi;
0034     __u64 lo;
0035     __u64 pc;
0036 };
0037
0038 /*
0039  * for KVM_GET_FPU and KVM_SET_FPU
0040  */
0041 struct kvm_fpu {
0042 };
0043
0044
0045 /*
0046  * For MIPS, we use KVM_SET_ONE_REG and KVM_GET_ONE_REG to access various
0047  * registers.  The id field is broken down as follows:
0048  *
0049  *  bits[63..52] - As per linux/kvm.h
0050  *  bits[51..32] - Must be zero.
0051  *  bits[31..16] - Register set.
0052  *
0053  * Register set = 0: GP registers from kvm_regs (see definitions below).
0054  *
0055  * Register set = 1: CP0 registers.
0056  *  bits[15..8]  - Must be zero.
0057  *  bits[7..3]   - Register 'rd'  index.
0058  *  bits[2..0]   - Register 'sel' index.
0059  *
0060  * Register set = 2: KVM specific registers (see definitions below).
0061  *
0062  * Register set = 3: FPU / MSA registers (see definitions below).
0063  *
0064  * Other sets registers may be added in the future.  Each set would
0065  * have its own identifier in bits[31..16].
0066  */
0067
0068 #define KVM_REG_MIPS_GP     (KVM_REG_MIPS | 0x0000000000000000ULL)
0069 #define KVM_REG_MIPS_CP0    (KVM_REG_MIPS | 0x0000000000010000ULL)
0070 #define KVM_REG_MIPS_KVM    (KVM_REG_MIPS | 0x0000000000020000ULL)
0071 #define KVM_REG_MIPS_FPU    (KVM_REG_MIPS | 0x0000000000030000ULL)
0072
0073
0074 /*
0075  * KVM_REG_MIPS_GP - General purpose registers from kvm_regs.
0076  */
0077
0078 #define KVM_REG_MIPS_R0     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  0)
0079 #define KVM_REG_MIPS_R1     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  1)
0080 #define KVM_REG_MIPS_R2     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  2)
0081 #define KVM_REG_MIPS_R3     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  3)
0082 #define KVM_REG_MIPS_R4     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  4)
0083 #define KVM_REG_MIPS_R5     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  5)
0084 #define KVM_REG_MIPS_R6     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  6)
0085 #define KVM_REG_MIPS_R7     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  7)
0086 #define KVM_REG_MIPS_R8     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  8)
0087 #define KVM_REG_MIPS_R9     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 |  9)
0088 #define KVM_REG_MIPS_R10    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 10)
0089 #define KVM_REG_MIPS_R11    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 11)
0090 #define KVM_REG_MIPS_R12    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 12)
0091 #define KVM_REG_MIPS_R13    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 13)
0092 #define KVM_REG_MIPS_R14    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 14)
0093 #define KVM_REG_MIPS_R15    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 15)
0094 #define KVM_REG_MIPS_R16    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 16)
0095 #define KVM_REG_MIPS_R17    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 17)
0096 #define KVM_REG_MIPS_R18    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 18)
0097 #define KVM_REG_MIPS_R19    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 19)
0098 #define KVM_REG_MIPS_R20    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 20)
0099 #define KVM_REG_MIPS_R21    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 21)
0100 #define KVM_REG_MIPS_R22    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 22)
0101 #define KVM_REG_MIPS_R23    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 23)
0102 #define KVM_REG_MIPS_R24    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 24)
0103 #define KVM_REG_MIPS_R25    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 25)
0104 #define KVM_REG_MIPS_R26    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 26)
0105 #define KVM_REG_MIPS_R27    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 27)
0106 #define KVM_REG_MIPS_R28    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 28)
0107 #define KVM_REG_MIPS_R29    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 29)
0108 #define KVM_REG_MIPS_R30    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 30)
0109 #define KVM_REG_MIPS_R31    (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 31)
0110
0111 #define KVM_REG_MIPS_HI     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 32)
0112 #define KVM_REG_MIPS_LO     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 33)
0113 #define KVM_REG_MIPS_PC     (KVM_REG_MIPS_GP | KVM_REG_SIZE_U64 | 34)
0114
0115
0116 /*
0117  * KVM_REG_MIPS_KVM - KVM specific control registers.
0118  */
0119
0120 /*
0121  * CP0_Count control
0122  * DC:    Set 0: Master disable CP0_Count and set COUNT_RESUME to now
0123  *        Set 1: Master re-enable CP0_Count with unchanged bias, handling timer
0124  *               interrupts since COUNT_RESUME
0125  *        This can be used to freeze the timer to get a consistent snapshot of
0126  *        the CP0_Count and timer interrupt pending state, while also resuming
0127  *        safely without losing time or guest timer interrupts.
0128  * Other: Reserved, do not change.
0129  */
0130 #define KVM_REG_MIPS_COUNT_CTL      (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 0)
0131 #define KVM_REG_MIPS_COUNT_CTL_DC   0x00000001
0132
0133 /*
0134  * CP0_Count resume monotonic nanoseconds
0135  * The monotonic nanosecond time of the last set of COUNT_CTL.DC (master
0136  * disable). Any reads and writes of Count related registers while
0137  * COUNT_CTL.DC=1 will appear to occur at this time. When COUNT_CTL.DC is
0138  * cleared again (master enable) any timer interrupts since this time will be
0139  * emulated.
0140  * Modifications to times in the future are rejected.
0141  */
0142 #define KVM_REG_MIPS_COUNT_RESUME   (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 1)
0143 /*
0144  * CP0_Count rate in Hz
0145  * Specifies the rate of the CP0_Count timer in Hz. Modifications occur without
0146  * discontinuities in CP0_Count.
0147  */
0148 #define KVM_REG_MIPS_COUNT_HZ       (KVM_REG_MIPS_KVM | KVM_REG_SIZE_U64 | 2)
0149
0150
0151 /*
0152  * KVM_REG_MIPS_FPU - Floating Point and MIPS SIMD Architecture (MSA) registers.
0153  *
0154  *  bits[15..8]  - Register subset (see definitions below).
0155  *  bits[7..5]   - Must be zero.
0156  *  bits[4..0]   - Register number within register subset.
0157  */
0158
0159 #define KVM_REG_MIPS_FPR    (KVM_REG_MIPS_FPU | 0x0000000000000000ULL)
0160 #define KVM_REG_MIPS_FCR    (KVM_REG_MIPS_FPU | 0x0000000000000100ULL)
0161 #define KVM_REG_MIPS_MSACR  (KVM_REG_MIPS_FPU | 0x0000000000000200ULL)
0162
0163 /*
0164  * KVM_REG_MIPS_FPR - Floating point / Vector registers.
0165  */
0166 #define KVM_REG_MIPS_FPR_32(n)  (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U32  | (n))
0167 #define KVM_REG_MIPS_FPR_64(n)  (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U64  | (n))
0168 #define KVM_REG_MIPS_VEC_128(n) (KVM_REG_MIPS_FPR | KVM_REG_SIZE_U128 | (n))
0169
0170 /*
0171  * KVM_REG_MIPS_FCR - Floating point control registers.
0172  */
0173 #define KVM_REG_MIPS_FCR_IR (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 |  0)
0174 #define KVM_REG_MIPS_FCR_CSR    (KVM_REG_MIPS_FCR | KVM_REG_SIZE_U32 | 31)
0175
0176 /*
0177  * KVM_REG_MIPS_MSACR - MIPS SIMD Architecture (MSA) control registers.
0178  */
0179 #define KVM_REG_MIPS_MSA_IR  (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  0)
0180 #define KVM_REG_MIPS_MSA_CSR     (KVM_REG_MIPS_MSACR | KVM_REG_SIZE_U32 |  1)
0181
0182
0183 /*
0184  * KVM MIPS specific structures and definitions
0185  *
0186  */
0187 struct kvm_debug_exit_arch {
0188     __u64 epc;
0189 };
0190
0191 /* for KVM_SET_GUEST_DEBUG */
0192 struct kvm_guest_debug_arch {
0193 };
0194
0195 /* definition of registers in kvm_run */
0196 struct kvm_sync_regs {
0197 };
0198
0199 /* dummy definition */
0200 struct kvm_sregs {
0201 };
0202
0203 struct kvm_mips_interrupt {
0204     /* in */
0205     __u32 cpu;
0206     __u32 irq;
0207 };
0208
0209 #endif /* __LINUX_KVM_MIPS_H */