0001
0002 #ifndef _ASM_ARM64_PERF_REGS_H
0003 #define _ASM_ARM64_PERF_REGS_H
0004
0005 enum perf_event_arm_regs {
0006 PERF_REG_ARM64_X0,
0007 PERF_REG_ARM64_X1,
0008 PERF_REG_ARM64_X2,
0009 PERF_REG_ARM64_X3,
0010 PERF_REG_ARM64_X4,
0011 PERF_REG_ARM64_X5,
0012 PERF_REG_ARM64_X6,
0013 PERF_REG_ARM64_X7,
0014 PERF_REG_ARM64_X8,
0015 PERF_REG_ARM64_X9,
0016 PERF_REG_ARM64_X10,
0017 PERF_REG_ARM64_X11,
0018 PERF_REG_ARM64_X12,
0019 PERF_REG_ARM64_X13,
0020 PERF_REG_ARM64_X14,
0021 PERF_REG_ARM64_X15,
0022 PERF_REG_ARM64_X16,
0023 PERF_REG_ARM64_X17,
0024 PERF_REG_ARM64_X18,
0025 PERF_REG_ARM64_X19,
0026 PERF_REG_ARM64_X20,
0027 PERF_REG_ARM64_X21,
0028 PERF_REG_ARM64_X22,
0029 PERF_REG_ARM64_X23,
0030 PERF_REG_ARM64_X24,
0031 PERF_REG_ARM64_X25,
0032 PERF_REG_ARM64_X26,
0033 PERF_REG_ARM64_X27,
0034 PERF_REG_ARM64_X28,
0035 PERF_REG_ARM64_X29,
0036 PERF_REG_ARM64_LR,
0037 PERF_REG_ARM64_SP,
0038 PERF_REG_ARM64_PC,
0039
0040
0041 PERF_REG_ARM64_VG = 46,
0042
0043 PERF_REG_ARM64_MAX = PERF_REG_ARM64_PC + 1,
0044 PERF_REG_ARM64_EXTENDED_MAX = PERF_REG_ARM64_VG + 1
0045 };
0046 #endif