0001
0002 #ifndef _ASM_ARM_PERF_REGS_H
0003 #define _ASM_ARM_PERF_REGS_H
0004
0005 enum perf_event_arm_regs {
0006 PERF_REG_ARM_R0,
0007 PERF_REG_ARM_R1,
0008 PERF_REG_ARM_R2,
0009 PERF_REG_ARM_R3,
0010 PERF_REG_ARM_R4,
0011 PERF_REG_ARM_R5,
0012 PERF_REG_ARM_R6,
0013 PERF_REG_ARM_R7,
0014 PERF_REG_ARM_R8,
0015 PERF_REG_ARM_R9,
0016 PERF_REG_ARM_R10,
0017 PERF_REG_ARM_FP,
0018 PERF_REG_ARM_IP,
0019 PERF_REG_ARM_SP,
0020 PERF_REG_ARM_LR,
0021 PERF_REG_ARM_PC,
0022 PERF_REG_ARM_MAX,
0023 };
0024 #endif