uapi/asm/kvm.h

0001 /* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
0002 /*
0003  * Copyright (C) 2012 - Virtual Open Systems and Columbia University
0004  * Author: Christoffer Dall <c.dall@virtualopensystems.com>
0005  *
0006  * This program is free software; you can redistribute it and/or modify
0007  * it under the terms of the GNU General Public License, version 2, as
0008  * published by the Free Software Foundation.
0009  *
0010  * This program is distributed in the hope that it will be useful,
0011  * but WITHOUT ANY WARRANTY; without even the implied warranty of
0012  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
0013  * GNU General Public License for more details.
0014  *
0015  * You should have received a copy of the GNU General Public License
0016  * along with this program; if not, write to the Free Software
0017  * Foundation, 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
0018  */
0019
0020 #ifndef __ARM_KVM_H__
0021 #define __ARM_KVM_H__
0022
0023 #include <linux/types.h>
0024 #include <linux/psci.h>
0025 #include <asm/ptrace.h>
0026
0027 #define __KVM_HAVE_GUEST_DEBUG
0028 #define __KVM_HAVE_IRQ_LINE
0029 #define __KVM_HAVE_READONLY_MEM
0030 #define __KVM_HAVE_VCPU_EVENTS
0031
0032 #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
0033
0034 #define KVM_REG_SIZE(id)                        \
0035     (1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
0036
0037 /* Valid for svc_regs, abt_regs, und_regs, irq_regs in struct kvm_regs */
0038 #define KVM_ARM_SVC_sp      svc_regs[0]
0039 #define KVM_ARM_SVC_lr      svc_regs[1]
0040 #define KVM_ARM_SVC_spsr    svc_regs[2]
0041 #define KVM_ARM_ABT_sp      abt_regs[0]
0042 #define KVM_ARM_ABT_lr      abt_regs[1]
0043 #define KVM_ARM_ABT_spsr    abt_regs[2]
0044 #define KVM_ARM_UND_sp      und_regs[0]
0045 #define KVM_ARM_UND_lr      und_regs[1]
0046 #define KVM_ARM_UND_spsr    und_regs[2]
0047 #define KVM_ARM_IRQ_sp      irq_regs[0]
0048 #define KVM_ARM_IRQ_lr      irq_regs[1]
0049 #define KVM_ARM_IRQ_spsr    irq_regs[2]
0050
0051 /* Valid only for fiq_regs in struct kvm_regs */
0052 #define KVM_ARM_FIQ_r8      fiq_regs[0]
0053 #define KVM_ARM_FIQ_r9      fiq_regs[1]
0054 #define KVM_ARM_FIQ_r10     fiq_regs[2]
0055 #define KVM_ARM_FIQ_fp      fiq_regs[3]
0056 #define KVM_ARM_FIQ_ip      fiq_regs[4]
0057 #define KVM_ARM_FIQ_sp      fiq_regs[5]
0058 #define KVM_ARM_FIQ_lr      fiq_regs[6]
0059 #define KVM_ARM_FIQ_spsr    fiq_regs[7]
0060
0061 struct kvm_regs {
0062     struct pt_regs usr_regs;    /* R0_usr - R14_usr, PC, CPSR */
0063     unsigned long svc_regs[3];  /* SP_svc, LR_svc, SPSR_svc */
0064     unsigned long abt_regs[3];  /* SP_abt, LR_abt, SPSR_abt */
0065     unsigned long und_regs[3];  /* SP_und, LR_und, SPSR_und */
0066     unsigned long irq_regs[3];  /* SP_irq, LR_irq, SPSR_irq */
0067     unsigned long fiq_regs[8];  /* R8_fiq - R14_fiq, SPSR_fiq */
0068 };
0069
0070 /* Supported Processor Types */
0071 #define KVM_ARM_TARGET_CORTEX_A15   0
0072 #define KVM_ARM_TARGET_CORTEX_A7    1
0073 #define KVM_ARM_NUM_TARGETS     2
0074
0075 /* KVM_ARM_SET_DEVICE_ADDR ioctl id encoding */
0076 #define KVM_ARM_DEVICE_TYPE_SHIFT   0
0077 #define KVM_ARM_DEVICE_TYPE_MASK    (0xffff << KVM_ARM_DEVICE_TYPE_SHIFT)
0078 #define KVM_ARM_DEVICE_ID_SHIFT     16
0079 #define KVM_ARM_DEVICE_ID_MASK      (0xffff << KVM_ARM_DEVICE_ID_SHIFT)
0080
0081 /* Supported device IDs */
0082 #define KVM_ARM_DEVICE_VGIC_V2      0
0083
0084 /* Supported VGIC address types  */
0085 #define KVM_VGIC_V2_ADDR_TYPE_DIST  0
0086 #define KVM_VGIC_V2_ADDR_TYPE_CPU   1
0087
0088 #define KVM_VGIC_V2_DIST_SIZE       0x1000
0089 #define KVM_VGIC_V2_CPU_SIZE        0x2000
0090
0091 /* Supported VGICv3 address types  */
0092 #define KVM_VGIC_V3_ADDR_TYPE_DIST  2
0093 #define KVM_VGIC_V3_ADDR_TYPE_REDIST    3
0094 #define KVM_VGIC_ITS_ADDR_TYPE      4
0095 #define KVM_VGIC_V3_ADDR_TYPE_REDIST_REGION 5
0096
0097 #define KVM_VGIC_V3_DIST_SIZE       SZ_64K
0098 #define KVM_VGIC_V3_REDIST_SIZE     (2 * SZ_64K)
0099 #define KVM_VGIC_V3_ITS_SIZE        (2 * SZ_64K)
0100
0101 #define KVM_ARM_VCPU_POWER_OFF      0 /* CPU is started in OFF state */
0102 #define KVM_ARM_VCPU_PSCI_0_2       1 /* CPU uses PSCI v0.2 */
0103
0104 struct kvm_vcpu_init {
0105     __u32 target;
0106     __u32 features[7];
0107 };
0108
0109 struct kvm_sregs {
0110 };
0111
0112 struct kvm_fpu {
0113 };
0114
0115 struct kvm_guest_debug_arch {
0116 };
0117
0118 struct kvm_debug_exit_arch {
0119 };
0120
0121 struct kvm_sync_regs {
0122     /* Used with KVM_CAP_ARM_USER_IRQ */
0123     __u64 device_irq_level;
0124 };
0125
0126 struct kvm_arch_memory_slot {
0127 };
0128
0129 /* for KVM_GET/SET_VCPU_EVENTS */
0130 struct kvm_vcpu_events {
0131     struct {
0132         __u8 serror_pending;
0133         __u8 serror_has_esr;
0134         __u8 ext_dabt_pending;
0135         /* Align it to 8 bytes */
0136         __u8 pad[5];
0137         __u64 serror_esr;
0138     } exception;
0139     __u32 reserved[12];
0140 };
0141
0142 /* If you need to interpret the index values, here is the key: */
0143 #define KVM_REG_ARM_COPROC_MASK     0x000000000FFF0000
0144 #define KVM_REG_ARM_COPROC_SHIFT    16
0145 #define KVM_REG_ARM_32_OPC2_MASK    0x0000000000000007
0146 #define KVM_REG_ARM_32_OPC2_SHIFT   0
0147 #define KVM_REG_ARM_OPC1_MASK       0x0000000000000078
0148 #define KVM_REG_ARM_OPC1_SHIFT      3
0149 #define KVM_REG_ARM_CRM_MASK        0x0000000000000780
0150 #define KVM_REG_ARM_CRM_SHIFT       7
0151 #define KVM_REG_ARM_32_CRN_MASK     0x0000000000007800
0152 #define KVM_REG_ARM_32_CRN_SHIFT    11
0153 /*
0154  * For KVM currently all guest registers are nonsecure, but we reserve a bit
0155  * in the encoding to distinguish secure from nonsecure for AArch32 system
0156  * registers that are banked by security. This is 1 for the secure banked
0157  * register, and 0 for the nonsecure banked register or if the register is
0158  * not banked by security.
0159  */
0160 #define KVM_REG_ARM_SECURE_MASK 0x0000000010000000
0161 #define KVM_REG_ARM_SECURE_SHIFT    28
0162
0163 #define ARM_CP15_REG_SHIFT_MASK(x,n) \
0164     (((x) << KVM_REG_ARM_ ## n ## _SHIFT) & KVM_REG_ARM_ ## n ## _MASK)
0165
0166 #define __ARM_CP15_REG(op1,crn,crm,op2) \
0167     (KVM_REG_ARM | (15 << KVM_REG_ARM_COPROC_SHIFT) | \
0168     ARM_CP15_REG_SHIFT_MASK(op1, OPC1) | \
0169     ARM_CP15_REG_SHIFT_MASK(crn, 32_CRN) | \
0170     ARM_CP15_REG_SHIFT_MASK(crm, CRM) | \
0171     ARM_CP15_REG_SHIFT_MASK(op2, 32_OPC2))
0172
0173 #define ARM_CP15_REG32(...) (__ARM_CP15_REG(__VA_ARGS__) | KVM_REG_SIZE_U32)
0174
0175 #define __ARM_CP15_REG64(op1,crm) \
0176     (__ARM_CP15_REG(op1, 0, crm, 0) | KVM_REG_SIZE_U64)
0177 #define ARM_CP15_REG64(...) __ARM_CP15_REG64(__VA_ARGS__)
0178
0179 /* PL1 Physical Timer Registers */
0180 #define KVM_REG_ARM_PTIMER_CTL      ARM_CP15_REG32(0, 14, 2, 1)
0181 #define KVM_REG_ARM_PTIMER_CNT      ARM_CP15_REG64(0, 14)
0182 #define KVM_REG_ARM_PTIMER_CVAL     ARM_CP15_REG64(2, 14)
0183
0184 /* Virtual Timer Registers */
0185 #define KVM_REG_ARM_TIMER_CTL       ARM_CP15_REG32(0, 14, 3, 1)
0186 #define KVM_REG_ARM_TIMER_CNT       ARM_CP15_REG64(1, 14)
0187 #define KVM_REG_ARM_TIMER_CVAL      ARM_CP15_REG64(3, 14)
0188
0189 /* Normal registers are mapped as coprocessor 16. */
0190 #define KVM_REG_ARM_CORE        (0x0010 << KVM_REG_ARM_COPROC_SHIFT)
0191 #define KVM_REG_ARM_CORE_REG(name)  (offsetof(struct kvm_regs, name) / 4)
0192
0193 /* Some registers need more space to represent values. */
0194 #define KVM_REG_ARM_DEMUX       (0x0011 << KVM_REG_ARM_COPROC_SHIFT)
0195 #define KVM_REG_ARM_DEMUX_ID_MASK   0x000000000000FF00
0196 #define KVM_REG_ARM_DEMUX_ID_SHIFT  8
0197 #define KVM_REG_ARM_DEMUX_ID_CCSIDR (0x00 << KVM_REG_ARM_DEMUX_ID_SHIFT)
0198 #define KVM_REG_ARM_DEMUX_VAL_MASK  0x00000000000000FF
0199 #define KVM_REG_ARM_DEMUX_VAL_SHIFT 0
0200
0201 /* VFP registers: we could overload CP10 like ARM does, but that's ugly. */
0202 #define KVM_REG_ARM_VFP         (0x0012 << KVM_REG_ARM_COPROC_SHIFT)
0203 #define KVM_REG_ARM_VFP_MASK        0x000000000000FFFF
0204 #define KVM_REG_ARM_VFP_BASE_REG    0x0
0205 #define KVM_REG_ARM_VFP_FPSID       0x1000
0206 #define KVM_REG_ARM_VFP_FPSCR       0x1001
0207 #define KVM_REG_ARM_VFP_MVFR1       0x1006
0208 #define KVM_REG_ARM_VFP_MVFR0       0x1007
0209 #define KVM_REG_ARM_VFP_FPEXC       0x1008
0210 #define KVM_REG_ARM_VFP_FPINST      0x1009
0211 #define KVM_REG_ARM_VFP_FPINST2     0x100A
0212
0213 /* KVM-as-firmware specific pseudo-registers */
0214 #define KVM_REG_ARM_FW          (0x0014 << KVM_REG_ARM_COPROC_SHIFT)
0215 #define KVM_REG_ARM_FW_REG(r)       (KVM_REG_ARM | KVM_REG_SIZE_U64 | \
0216                      KVM_REG_ARM_FW | ((r) & 0xffff))
0217 #define KVM_REG_ARM_PSCI_VERSION    KVM_REG_ARM_FW_REG(0)
0218 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1 KVM_REG_ARM_FW_REG(1)
0219     /* Higher values mean better protection. */
0220 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_AVAIL       0
0221 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_AVAIL       1
0222 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_1_NOT_REQUIRED    2
0223 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2 KVM_REG_ARM_FW_REG(2)
0224     /* Higher values mean better protection. */
0225 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_AVAIL       0
0226 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_UNKNOWN     1
0227 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_AVAIL       2
0228 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_NOT_REQUIRED    3
0229 #define KVM_REG_ARM_SMCCC_ARCH_WORKAROUND_2_ENABLED (1U << 4)
0230
0231 /* Device Control API: ARM VGIC */
0232 #define KVM_DEV_ARM_VGIC_GRP_ADDR   0
0233 #define KVM_DEV_ARM_VGIC_GRP_DIST_REGS  1
0234 #define KVM_DEV_ARM_VGIC_GRP_CPU_REGS   2
0235 #define   KVM_DEV_ARM_VGIC_CPUID_SHIFT  32
0236 #define   KVM_DEV_ARM_VGIC_CPUID_MASK   (0xffULL << KVM_DEV_ARM_VGIC_CPUID_SHIFT)
0237 #define   KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT 32
0238 #define   KVM_DEV_ARM_VGIC_V3_MPIDR_MASK \
0239             (0xffffffffULL << KVM_DEV_ARM_VGIC_V3_MPIDR_SHIFT)
0240 #define   KVM_DEV_ARM_VGIC_OFFSET_SHIFT 0
0241 #define   KVM_DEV_ARM_VGIC_OFFSET_MASK  (0xffffffffULL << KVM_DEV_ARM_VGIC_OFFSET_SHIFT)
0242 #define   KVM_DEV_ARM_VGIC_SYSREG_INSTR_MASK (0xffff)
0243 #define KVM_DEV_ARM_VGIC_GRP_NR_IRQS    3
0244 #define KVM_DEV_ARM_VGIC_GRP_CTRL       4
0245 #define KVM_DEV_ARM_VGIC_GRP_REDIST_REGS 5
0246 #define KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS 6
0247 #define KVM_DEV_ARM_VGIC_GRP_LEVEL_INFO  7
0248 #define KVM_DEV_ARM_VGIC_GRP_ITS_REGS   8
0249 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT  10
0250 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_MASK \
0251             (0x3fffffULL << KVM_DEV_ARM_VGIC_LINE_LEVEL_INFO_SHIFT)
0252 #define KVM_DEV_ARM_VGIC_LINE_LEVEL_INTID_MASK 0x3ff
0253 #define VGIC_LEVEL_INFO_LINE_LEVEL  0
0254
0255 /* Device Control API on vcpu fd */
0256 #define KVM_ARM_VCPU_PMU_V3_CTRL    0
0257 #define   KVM_ARM_VCPU_PMU_V3_IRQ   0
0258 #define   KVM_ARM_VCPU_PMU_V3_INIT  1
0259 #define KVM_ARM_VCPU_TIMER_CTRL     1
0260 #define   KVM_ARM_VCPU_TIMER_IRQ_VTIMER     0
0261 #define   KVM_ARM_VCPU_TIMER_IRQ_PTIMER     1
0262
0263 #define   KVM_DEV_ARM_VGIC_CTRL_INIT        0
0264 #define   KVM_DEV_ARM_ITS_SAVE_TABLES       1
0265 #define   KVM_DEV_ARM_ITS_RESTORE_TABLES    2
0266 #define   KVM_DEV_ARM_VGIC_SAVE_PENDING_TABLES  3
0267 #define   KVM_DEV_ARM_ITS_CTRL_RESET        4
0268
0269 /* KVM_IRQ_LINE irq field index values */
0270 #define KVM_ARM_IRQ_VCPU2_SHIFT     28
0271 #define KVM_ARM_IRQ_VCPU2_MASK      0xf
0272 #define KVM_ARM_IRQ_TYPE_SHIFT      24
0273 #define KVM_ARM_IRQ_TYPE_MASK       0xf
0274 #define KVM_ARM_IRQ_VCPU_SHIFT      16
0275 #define KVM_ARM_IRQ_VCPU_MASK       0xff
0276 #define KVM_ARM_IRQ_NUM_SHIFT       0
0277 #define KVM_ARM_IRQ_NUM_MASK        0xffff
0278
0279 /* irq_type field */
0280 #define KVM_ARM_IRQ_TYPE_CPU        0
0281 #define KVM_ARM_IRQ_TYPE_SPI        1
0282 #define KVM_ARM_IRQ_TYPE_PPI        2
0283
0284 /* out-of-kernel GIC cpu interrupt injection irq_number field */
0285 #define KVM_ARM_IRQ_CPU_IRQ     0
0286 #define KVM_ARM_IRQ_CPU_FIQ     1
0287
0288 /*
0289  * This used to hold the highest supported SPI, but it is now obsolete
0290  * and only here to provide source code level compatibility with older
0291  * userland. The highest SPI number can be set via KVM_DEV_ARM_VGIC_GRP_NR_IRQS.
0292  */
0293 #ifndef __KERNEL__
0294 #define KVM_ARM_IRQ_GIC_MAX     127
0295 #endif
0296
0297 /* One single KVM irqchip, ie. the VGIC */
0298 #define KVM_NR_IRQCHIPS          1
0299
0300 /* PSCI interface */
0301 #define KVM_PSCI_FN_BASE        0x95c1ba5e
0302 #define KVM_PSCI_FN(n)          (KVM_PSCI_FN_BASE + (n))
0303
0304 #define KVM_PSCI_FN_CPU_SUSPEND     KVM_PSCI_FN(0)
0305 #define KVM_PSCI_FN_CPU_OFF     KVM_PSCI_FN(1)
0306 #define KVM_PSCI_FN_CPU_ON      KVM_PSCI_FN(2)
0307 #define KVM_PSCI_FN_MIGRATE     KVM_PSCI_FN(3)
0308
0309 #define KVM_PSCI_RET_SUCCESS        PSCI_RET_SUCCESS
0310 #define KVM_PSCI_RET_NI         PSCI_RET_NOT_SUPPORTED
0311 #define KVM_PSCI_RET_INVAL      PSCI_RET_INVALID_PARAMS
0312 #define KVM_PSCI_RET_DENIED     PSCI_RET_DENIED
0313
0314 #endif /* __ARM_KVM_H__ */