sound/x86/intel_hdmi_lpe_audio.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *   intel_hdmi_lpe_audio.h - Intel HDMI LPE audio driver
0004  *
0005  *  Copyright (C) 2016 Intel Corp
0006  *  Authors:    Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
0007  *      Ramesh Babu K V <ramesh.babu@intel.com>
0008  *      Vaibhav Agarwal <vaibhav.agarwal@intel.com>
0009  *      Jerome Anand <jerome.anand@intel.com>
0010  *      Aravind Siddappaji <aravindx.siddappaji@intel.com>
0011  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0012  *
0013  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0014  */
0015 #ifndef __INTEL_HDMI_LPE_AUDIO_H
0016 #define __INTEL_HDMI_LPE_AUDIO_H
0017
0018 #define HAD_MIN_CHANNEL     2
0019 #define HAD_MAX_CHANNEL     8
0020 #define HAD_NUM_OF_RING_BUFS    4
0021
0022 /* max 20bit address, aligned to 64 */
0023 #define HAD_MAX_BUFFER      ((1024 * 1024 - 1) & ~0x3f)
0024 #define HAD_DEFAULT_BUFFER  (600 * 1024) /* default prealloc size */
0025 #define HAD_MAX_PERIODS     256 /* arbitrary, but should suffice */
0026 #define HAD_MIN_PERIODS     1
0027 #define HAD_MAX_PERIOD_BYTES    ((HAD_MAX_BUFFER / HAD_MIN_PERIODS) & ~0x3f)
0028 #define HAD_MIN_PERIOD_BYTES    1024    /* might be smaller */
0029 #define HAD_FIFO_SIZE       0 /* fifo not being used */
0030 #define MAX_SPEAKERS        8
0031
0032 #define AUD_SAMPLE_RATE_32  32000
0033 #define AUD_SAMPLE_RATE_44_1    44100
0034 #define AUD_SAMPLE_RATE_48  48000
0035 #define AUD_SAMPLE_RATE_88_2    88200
0036 #define AUD_SAMPLE_RATE_96  96000
0037 #define AUD_SAMPLE_RATE_176_4   176400
0038 #define AUD_SAMPLE_RATE_192 192000
0039
0040 #define HAD_MIN_RATE        AUD_SAMPLE_RATE_32
0041 #define HAD_MAX_RATE        AUD_SAMPLE_RATE_192
0042
0043 #define DIS_SAMPLE_RATE_25_2    25200
0044 #define DIS_SAMPLE_RATE_27  27000
0045 #define DIS_SAMPLE_RATE_54  54000
0046 #define DIS_SAMPLE_RATE_74_25   74250
0047 #define DIS_SAMPLE_RATE_148_5   148500
0048 #define HAD_REG_WIDTH       0x08
0049 #define HAD_MAX_DIP_WORDS       16
0050
0051 /* DP Link Rates */
0052 #define DP_2_7_GHZ          270000
0053 #define DP_1_62_GHZ         162000
0054
0055 /* Maud Values */
0056 #define AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL      1988
0057 #define AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL        2740
0058 #define AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL      2982
0059 #define AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL        5480
0060 #define AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL      5965
0061 #define AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL       10961
0062 #define HAD_MAX_RATE_DP_2_7_MAUD_VAL            11930
0063 #define AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL     3314
0064 #define AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL       4567
0065 #define AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL     4971
0066 #define AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL       9134
0067 #define AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL     9942
0068 #define AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL      18268
0069 #define HAD_MAX_RATE_DP_1_62_MAUD_VAL           19884
0070
0071 /* Naud Value */
0072 #define DP_NAUD_VAL                 32768
0073
0074 /* HDMI Controller register offsets - audio domain common */
0075 /* Base address for below regs = 0x65000 */
0076 enum hdmi_ctrl_reg_offset_common {
0077     AUDIO_HDMI_CONFIG_A = 0x000,
0078     AUDIO_HDMI_CONFIG_B = 0x800,
0079     AUDIO_HDMI_CONFIG_C = 0x900,
0080 };
0081 /* HDMI controller register offsets */
0082 enum hdmi_ctrl_reg_offset {
0083     AUD_CONFIG      = 0x0,
0084     AUD_CH_STATUS_0     = 0x08,
0085     AUD_CH_STATUS_1     = 0x0C,
0086     AUD_HDMI_CTS        = 0x10,
0087     AUD_N_ENABLE        = 0x14,
0088     AUD_SAMPLE_RATE     = 0x18,
0089     AUD_BUF_CONFIG      = 0x20,
0090     AUD_BUF_CH_SWAP     = 0x24,
0091     AUD_BUF_A_ADDR      = 0x40,
0092     AUD_BUF_A_LENGTH    = 0x44,
0093     AUD_BUF_B_ADDR      = 0x48,
0094     AUD_BUF_B_LENGTH    = 0x4c,
0095     AUD_BUF_C_ADDR      = 0x50,
0096     AUD_BUF_C_LENGTH    = 0x54,
0097     AUD_BUF_D_ADDR      = 0x58,
0098     AUD_BUF_D_LENGTH    = 0x5c,
0099     AUD_CNTL_ST     = 0x60,
0100     AUD_HDMI_STATUS     = 0x64, /* v2 */
0101     AUD_HDMIW_INFOFR    = 0x68, /* v2 */
0102 };
0103
0104 /* Audio configuration */
0105 union aud_cfg {
0106     struct {
0107         u32 aud_en:1;
0108         u32 layout:1;       /* LAYOUT[01], see below */
0109         u32 fmt:2;
0110         u32 num_ch:3;
0111         u32 set:1;
0112         u32 flat:1;
0113         u32 val_bit:1;
0114         u32 user_bit:1;
0115         u32 underrun:1;     /* 0: send null packets,
0116                      * 1: send silence stream
0117                      */
0118         u32 packet_mode:1;  /* 0: 32bit container, 1: 16bit */
0119         u32 left_align:1;   /* 0: MSB bits 0-23, 1: bits 8-31 */
0120         u32 bogus_sample:1; /* bogus sample for odd channels */
0121         u32 dp_modei:1;     /* 0: HDMI, 1: DP */
0122         u32 rsvd:16;
0123     } regx;
0124     u32 regval;
0125 };
0126
0127 #define AUD_CONFIG_VALID_BIT            (1 << 9)
0128 #define AUD_CONFIG_DP_MODE          (1 << 15)
0129 #define AUD_CONFIG_CH_MASK  0x70
0130 #define LAYOUT0         0       /* interleaved stereo */
0131 #define LAYOUT1         1       /* for channels > 2 */
0132
0133 /* Audio Channel Status 0 Attributes */
0134 union aud_ch_status_0 {
0135     struct {
0136         u32 ch_status:1;
0137         u32 lpcm_id:1;
0138         u32 cp_info:1;
0139         u32 format:3;
0140         u32 mode:2;
0141         u32 ctg_code:8;
0142         u32 src_num:4;
0143         u32 ch_num:4;
0144         u32 samp_freq:4;    /* CH_STATUS_MAP_XXX */
0145         u32 clk_acc:2;
0146         u32 rsvd:2;
0147     } regx;
0148     u32 regval;
0149 };
0150
0151 /* samp_freq values - Sampling rate as per IEC60958 Ver 3 */
0152 #define CH_STATUS_MAP_32KHZ 0x3
0153 #define CH_STATUS_MAP_44KHZ 0x0
0154 #define CH_STATUS_MAP_48KHZ 0x2
0155 #define CH_STATUS_MAP_88KHZ 0x8
0156 #define CH_STATUS_MAP_96KHZ 0xA
0157 #define CH_STATUS_MAP_176KHZ    0xC
0158 #define CH_STATUS_MAP_192KHZ    0xE
0159
0160 /* Audio Channel Status 1 Attributes */
0161 union aud_ch_status_1 {
0162     struct {
0163         u32 max_wrd_len:1;
0164         u32 wrd_len:3;
0165         u32 rsvd:28;
0166     } regx;
0167     u32 regval;
0168 };
0169
0170 #define MAX_SMPL_WIDTH_20   0x0
0171 #define MAX_SMPL_WIDTH_24   0x1
0172 #define SMPL_WIDTH_16BITS   0x1
0173 #define SMPL_WIDTH_24BITS   0x5
0174
0175 /* CTS register */
0176 union aud_hdmi_cts {
0177     struct {
0178         u32 cts_val:24;
0179         u32 en_cts_prog:1;
0180         u32 rsvd:7;
0181     } regx;
0182     u32 regval;
0183 };
0184
0185 /* N register */
0186 union aud_hdmi_n_enable {
0187     struct {
0188         u32 n_val:24;
0189         u32 en_n_prog:1;
0190         u32 rsvd:7;
0191     } regx;
0192     u32 regval;
0193 };
0194
0195 /* Audio Buffer configurations */
0196 union aud_buf_config {
0197     struct {
0198         u32 audio_fifo_watermark:8;
0199         u32 dma_fifo_watermark:3;
0200         u32 rsvd0:5;
0201         u32 aud_delay:8;
0202         u32 rsvd1:8;
0203     } regx;
0204     u32 regval;
0205 };
0206
0207 #define FIFO_THRESHOLD      0xFE
0208 #define DMA_FIFO_THRESHOLD  0x7
0209
0210 /* Audio Sample Swapping offset */
0211 union aud_buf_ch_swap {
0212     struct {
0213         u32 first_0:3;
0214         u32 second_0:3;
0215         u32 first_1:3;
0216         u32 second_1:3;
0217         u32 first_2:3;
0218         u32 second_2:3;
0219         u32 first_3:3;
0220         u32 second_3:3;
0221         u32 rsvd:8;
0222     } regx;
0223     u32 regval;
0224 };
0225
0226 #define SWAP_LFE_CENTER     0x00fac4c8  /* octal 76543210 */
0227
0228 /* Address for Audio Buffer */
0229 union aud_buf_addr {
0230     struct {
0231         u32 valid:1;
0232         u32 intr_en:1;
0233         u32 rsvd:4;
0234         u32 addr:26;
0235     } regx;
0236     u32 regval;
0237 };
0238
0239 #define AUD_BUF_VALID       (1U << 0)
0240 #define AUD_BUF_INTR_EN     (1U << 1)
0241
0242 /* Length of Audio Buffer */
0243 union aud_buf_len {
0244     struct {
0245         u32 buf_len:20;
0246         u32 rsvd:12;
0247     } regx;
0248     u32 regval;
0249 };
0250
0251 /* Audio Control State Register offset */
0252 union aud_ctrl_st {
0253     struct {
0254         u32 ram_addr:4;
0255         u32 eld_ack:1;
0256         u32 eld_addr:4;
0257         u32 eld_buf_size:5;
0258         u32 eld_valid:1;
0259         u32 cp_ready:1;
0260         u32 dip_freq:2;
0261         u32 dip_idx:3;
0262         u32 dip_en_sta:4;
0263         u32 rsvd:7;
0264     } regx;
0265     u32 regval;
0266 };
0267
0268 /* Audio HDMI Widget Data Island Packet offset */
0269 union aud_info_frame1 {
0270     struct {
0271         u32 pkt_type:8;
0272         u32 ver_num:8;
0273         u32 len:5;
0274         u32 rsvd:11;
0275     } regx;
0276     u32 regval;
0277 };
0278
0279 #define HDMI_INFO_FRAME_WORD1   0x000a0184
0280 #define DP_INFO_FRAME_WORD1 0x00441b84
0281
0282 /* DIP frame 2 */
0283 union aud_info_frame2 {
0284     struct {
0285         u32 chksum:8;
0286         u32 chnl_cnt:3;
0287         u32 rsvd0:1;
0288         u32 coding_type:4;
0289         u32 smpl_size:2;
0290         u32 smpl_freq:3;
0291         u32 rsvd1:3;
0292         u32 format:8;
0293     } regx;
0294     u32 regval;
0295 };
0296
0297 /* DIP frame 3 */
0298 union aud_info_frame3 {
0299     struct {
0300         u32 chnl_alloc:8;
0301         u32 rsvd0:3;
0302         u32 lsv:4;
0303         u32 dm_inh:1;
0304         u32 rsvd1:16;
0305     } regx;
0306     u32 regval;
0307 };
0308
0309 #define VALID_DIP_WORDS     3
0310
0311 /* AUD_HDMI_STATUS bits */
0312 #define HDMI_AUDIO_UNDERRUN     (1U << 31)
0313 #define HDMI_AUDIO_BUFFER_DONE      (1U << 29)
0314
0315 /* AUD_HDMI_STATUS register mask */
0316 #define AUD_HDMI_STATUS_MASK_UNDERRUN   0xC0000000
0317 #define AUD_HDMI_STATUS_MASK_SRDBG  0x00000002
0318 #define AUD_HDMI_STATUSG_MASK_FUNCRST   0x00000001
0319
0320 #endif