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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  *   intel_hdmi_audio.c - Intel HDMI audio driver
0004  *
0005  *  Copyright (C) 2016 Intel Corp
0006  *  Authors:    Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>
0007  *      Ramesh Babu K V <ramesh.babu@intel.com>
0008  *      Vaibhav Agarwal <vaibhav.agarwal@intel.com>
0009  *      Jerome Anand <jerome.anand@intel.com>
0010  *  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0011  *
0012  * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
0013  * ALSA driver for Intel HDMI audio
0014  */
0015 
0016 #include <linux/types.h>
0017 #include <linux/platform_device.h>
0018 #include <linux/io.h>
0019 #include <linux/slab.h>
0020 #include <linux/module.h>
0021 #include <linux/interrupt.h>
0022 #include <linux/pm_runtime.h>
0023 #include <linux/dma-mapping.h>
0024 #include <linux/delay.h>
0025 #include <sound/core.h>
0026 #include <sound/asoundef.h>
0027 #include <sound/pcm.h>
0028 #include <sound/pcm_params.h>
0029 #include <sound/initval.h>
0030 #include <sound/control.h>
0031 #include <sound/jack.h>
0032 #include <drm/drm_edid.h>
0033 #include <drm/intel_lpe_audio.h>
0034 #include "intel_hdmi_audio.h"
0035 
0036 #define INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS  5000
0037 
0038 #define for_each_pipe(card_ctx, pipe) \
0039     for ((pipe) = 0; (pipe) < (card_ctx)->num_pipes; (pipe)++)
0040 #define for_each_port(card_ctx, port) \
0041     for ((port) = 0; (port) < (card_ctx)->num_ports; (port)++)
0042 
0043 /*standard module options for ALSA. This module supports only one card*/
0044 static int hdmi_card_index = SNDRV_DEFAULT_IDX1;
0045 static char *hdmi_card_id = SNDRV_DEFAULT_STR1;
0046 static bool single_port;
0047 
0048 module_param_named(index, hdmi_card_index, int, 0444);
0049 MODULE_PARM_DESC(index,
0050         "Index value for INTEL Intel HDMI Audio controller.");
0051 module_param_named(id, hdmi_card_id, charp, 0444);
0052 MODULE_PARM_DESC(id,
0053         "ID string for INTEL Intel HDMI Audio controller.");
0054 module_param(single_port, bool, 0444);
0055 MODULE_PARM_DESC(single_port,
0056         "Single-port mode (for compatibility)");
0057 
0058 /*
0059  * ELD SA bits in the CEA Speaker Allocation data block
0060  */
0061 static const int eld_speaker_allocation_bits[] = {
0062     [0] = FL | FR,
0063     [1] = LFE,
0064     [2] = FC,
0065     [3] = RL | RR,
0066     [4] = RC,
0067     [5] = FLC | FRC,
0068     [6] = RLC | RRC,
0069     /* the following are not defined in ELD yet */
0070     [7] = 0,
0071 };
0072 
0073 /*
0074  * This is an ordered list!
0075  *
0076  * The preceding ones have better chances to be selected by
0077  * hdmi_channel_allocation().
0078  */
0079 static struct cea_channel_speaker_allocation channel_allocations[] = {
0080 /*                        channel:   7     6    5    4    3     2    1    0  */
0081 { .ca_index = 0x00,  .speakers = {   0,    0,   0,   0,   0,    0,  FR,  FL } },
0082                 /* 2.1 */
0083 { .ca_index = 0x01,  .speakers = {   0,    0,   0,   0,   0,  LFE,  FR,  FL } },
0084                 /* Dolby Surround */
0085 { .ca_index = 0x02,  .speakers = {   0,    0,   0,   0,  FC,    0,  FR,  FL } },
0086                 /* surround40 */
0087 { .ca_index = 0x08,  .speakers = {   0,    0,  RR,  RL,   0,    0,  FR,  FL } },
0088                 /* surround41 */
0089 { .ca_index = 0x09,  .speakers = {   0,    0,  RR,  RL,   0,  LFE,  FR,  FL } },
0090                 /* surround50 */
0091 { .ca_index = 0x0a,  .speakers = {   0,    0,  RR,  RL,  FC,    0,  FR,  FL } },
0092                 /* surround51 */
0093 { .ca_index = 0x0b,  .speakers = {   0,    0,  RR,  RL,  FC,  LFE,  FR,  FL } },
0094                 /* 6.1 */
0095 { .ca_index = 0x0f,  .speakers = {   0,   RC,  RR,  RL,  FC,  LFE,  FR,  FL } },
0096                 /* surround71 */
0097 { .ca_index = 0x13,  .speakers = { RRC,  RLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
0098 
0099 { .ca_index = 0x03,  .speakers = {   0,    0,   0,   0,  FC,  LFE,  FR,  FL } },
0100 { .ca_index = 0x04,  .speakers = {   0,    0,   0,  RC,   0,    0,  FR,  FL } },
0101 { .ca_index = 0x05,  .speakers = {   0,    0,   0,  RC,   0,  LFE,  FR,  FL } },
0102 { .ca_index = 0x06,  .speakers = {   0,    0,   0,  RC,  FC,    0,  FR,  FL } },
0103 { .ca_index = 0x07,  .speakers = {   0,    0,   0,  RC,  FC,  LFE,  FR,  FL } },
0104 { .ca_index = 0x0c,  .speakers = {   0,   RC,  RR,  RL,   0,    0,  FR,  FL } },
0105 { .ca_index = 0x0d,  .speakers = {   0,   RC,  RR,  RL,   0,  LFE,  FR,  FL } },
0106 { .ca_index = 0x0e,  .speakers = {   0,   RC,  RR,  RL,  FC,    0,  FR,  FL } },
0107 { .ca_index = 0x10,  .speakers = { RRC,  RLC,  RR,  RL,   0,    0,  FR,  FL } },
0108 { .ca_index = 0x11,  .speakers = { RRC,  RLC,  RR,  RL,   0,  LFE,  FR,  FL } },
0109 { .ca_index = 0x12,  .speakers = { RRC,  RLC,  RR,  RL,  FC,    0,  FR,  FL } },
0110 { .ca_index = 0x14,  .speakers = { FRC,  FLC,   0,   0,   0,    0,  FR,  FL } },
0111 { .ca_index = 0x15,  .speakers = { FRC,  FLC,   0,   0,   0,  LFE,  FR,  FL } },
0112 { .ca_index = 0x16,  .speakers = { FRC,  FLC,   0,   0,  FC,    0,  FR,  FL } },
0113 { .ca_index = 0x17,  .speakers = { FRC,  FLC,   0,   0,  FC,  LFE,  FR,  FL } },
0114 { .ca_index = 0x18,  .speakers = { FRC,  FLC,   0,  RC,   0,    0,  FR,  FL } },
0115 { .ca_index = 0x19,  .speakers = { FRC,  FLC,   0,  RC,   0,  LFE,  FR,  FL } },
0116 { .ca_index = 0x1a,  .speakers = { FRC,  FLC,   0,  RC,  FC,    0,  FR,  FL } },
0117 { .ca_index = 0x1b,  .speakers = { FRC,  FLC,   0,  RC,  FC,  LFE,  FR,  FL } },
0118 { .ca_index = 0x1c,  .speakers = { FRC,  FLC,  RR,  RL,   0,    0,  FR,  FL } },
0119 { .ca_index = 0x1d,  .speakers = { FRC,  FLC,  RR,  RL,   0,  LFE,  FR,  FL } },
0120 { .ca_index = 0x1e,  .speakers = { FRC,  FLC,  RR,  RL,  FC,    0,  FR,  FL } },
0121 { .ca_index = 0x1f,  .speakers = { FRC,  FLC,  RR,  RL,  FC,  LFE,  FR,  FL } },
0122 };
0123 
0124 static const struct channel_map_table map_tables[] = {
0125     { SNDRV_CHMAP_FL,       0x00,   FL },
0126     { SNDRV_CHMAP_FR,       0x01,   FR },
0127     { SNDRV_CHMAP_RL,       0x04,   RL },
0128     { SNDRV_CHMAP_RR,       0x05,   RR },
0129     { SNDRV_CHMAP_LFE,      0x02,   LFE },
0130     { SNDRV_CHMAP_FC,       0x03,   FC },
0131     { SNDRV_CHMAP_RLC,      0x06,   RLC },
0132     { SNDRV_CHMAP_RRC,      0x07,   RRC },
0133     {} /* terminator */
0134 };
0135 
0136 /* hardware capability structure */
0137 static const struct snd_pcm_hardware had_pcm_hardware = {
0138     .info = (SNDRV_PCM_INFO_INTERLEAVED |
0139         SNDRV_PCM_INFO_MMAP |
0140         SNDRV_PCM_INFO_MMAP_VALID |
0141         SNDRV_PCM_INFO_NO_PERIOD_WAKEUP),
0142     .formats = (SNDRV_PCM_FMTBIT_S16_LE |
0143             SNDRV_PCM_FMTBIT_S24_LE |
0144             SNDRV_PCM_FMTBIT_S32_LE),
0145     .rates = SNDRV_PCM_RATE_32000 |
0146         SNDRV_PCM_RATE_44100 |
0147         SNDRV_PCM_RATE_48000 |
0148         SNDRV_PCM_RATE_88200 |
0149         SNDRV_PCM_RATE_96000 |
0150         SNDRV_PCM_RATE_176400 |
0151         SNDRV_PCM_RATE_192000,
0152     .rate_min = HAD_MIN_RATE,
0153     .rate_max = HAD_MAX_RATE,
0154     .channels_min = HAD_MIN_CHANNEL,
0155     .channels_max = HAD_MAX_CHANNEL,
0156     .buffer_bytes_max = HAD_MAX_BUFFER,
0157     .period_bytes_min = HAD_MIN_PERIOD_BYTES,
0158     .period_bytes_max = HAD_MAX_PERIOD_BYTES,
0159     .periods_min = HAD_MIN_PERIODS,
0160     .periods_max = HAD_MAX_PERIODS,
0161     .fifo_size = HAD_FIFO_SIZE,
0162 };
0163 
0164 /* Get the active PCM substream;
0165  * Call had_substream_put() for unreferecing.
0166  * Don't call this inside had_spinlock, as it takes by itself
0167  */
0168 static struct snd_pcm_substream *
0169 had_substream_get(struct snd_intelhad *intelhaddata)
0170 {
0171     struct snd_pcm_substream *substream;
0172     unsigned long flags;
0173 
0174     spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
0175     substream = intelhaddata->stream_info.substream;
0176     if (substream)
0177         intelhaddata->stream_info.substream_refcount++;
0178     spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
0179     return substream;
0180 }
0181 
0182 /* Unref the active PCM substream;
0183  * Don't call this inside had_spinlock, as it takes by itself
0184  */
0185 static void had_substream_put(struct snd_intelhad *intelhaddata)
0186 {
0187     unsigned long flags;
0188 
0189     spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
0190     intelhaddata->stream_info.substream_refcount--;
0191     spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
0192 }
0193 
0194 static u32 had_config_offset(int pipe)
0195 {
0196     switch (pipe) {
0197     default:
0198     case 0:
0199         return AUDIO_HDMI_CONFIG_A;
0200     case 1:
0201         return AUDIO_HDMI_CONFIG_B;
0202     case 2:
0203         return AUDIO_HDMI_CONFIG_C;
0204     }
0205 }
0206 
0207 /* Register access functions */
0208 static u32 had_read_register_raw(struct snd_intelhad_card *card_ctx,
0209                  int pipe, u32 reg)
0210 {
0211     return ioread32(card_ctx->mmio_start + had_config_offset(pipe) + reg);
0212 }
0213 
0214 static void had_write_register_raw(struct snd_intelhad_card *card_ctx,
0215                    int pipe, u32 reg, u32 val)
0216 {
0217     iowrite32(val, card_ctx->mmio_start + had_config_offset(pipe) + reg);
0218 }
0219 
0220 static void had_read_register(struct snd_intelhad *ctx, u32 reg, u32 *val)
0221 {
0222     if (!ctx->connected)
0223         *val = 0;
0224     else
0225         *val = had_read_register_raw(ctx->card_ctx, ctx->pipe, reg);
0226 }
0227 
0228 static void had_write_register(struct snd_intelhad *ctx, u32 reg, u32 val)
0229 {
0230     if (ctx->connected)
0231         had_write_register_raw(ctx->card_ctx, ctx->pipe, reg, val);
0232 }
0233 
0234 /*
0235  * enable / disable audio configuration
0236  *
0237  * The normal read/modify should not directly be used on VLV2 for
0238  * updating AUD_CONFIG register.
0239  * This is because:
0240  * Bit6 of AUD_CONFIG register is writeonly due to a silicon bug on VLV2
0241  * HDMI IP. As a result a read-modify of AUD_CONFIG register will always
0242  * clear bit6. AUD_CONFIG[6:4] represents the "channels" field of the
0243  * register. This field should be 1xy binary for configuration with 6 or
0244  * more channels. Read-modify of AUD_CONFIG (Eg. for enabling audio)
0245  * causes the "channels" field to be updated as 0xy binary resulting in
0246  * bad audio. The fix is to always write the AUD_CONFIG[6:4] with
0247  * appropriate value when doing read-modify of AUD_CONFIG register.
0248  */
0249 static void had_enable_audio(struct snd_intelhad *intelhaddata,
0250                  bool enable)
0251 {
0252     /* update the cached value */
0253     intelhaddata->aud_config.regx.aud_en = enable;
0254     had_write_register(intelhaddata, AUD_CONFIG,
0255                intelhaddata->aud_config.regval);
0256 }
0257 
0258 /* forcibly ACKs to both BUFFER_DONE and BUFFER_UNDERRUN interrupts */
0259 static void had_ack_irqs(struct snd_intelhad *ctx)
0260 {
0261     u32 status_reg;
0262 
0263     if (!ctx->connected)
0264         return;
0265     had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
0266     status_reg |= HDMI_AUDIO_BUFFER_DONE | HDMI_AUDIO_UNDERRUN;
0267     had_write_register(ctx, AUD_HDMI_STATUS, status_reg);
0268     had_read_register(ctx, AUD_HDMI_STATUS, &status_reg);
0269 }
0270 
0271 /* Reset buffer pointers */
0272 static void had_reset_audio(struct snd_intelhad *intelhaddata)
0273 {
0274     had_write_register(intelhaddata, AUD_HDMI_STATUS,
0275                AUD_HDMI_STATUSG_MASK_FUNCRST);
0276     had_write_register(intelhaddata, AUD_HDMI_STATUS, 0);
0277 }
0278 
0279 /*
0280  * initialize audio channel status registers
0281  * This function is called in the prepare callback
0282  */
0283 static int had_prog_status_reg(struct snd_pcm_substream *substream,
0284             struct snd_intelhad *intelhaddata)
0285 {
0286     union aud_ch_status_0 ch_stat0 = {.regval = 0};
0287     union aud_ch_status_1 ch_stat1 = {.regval = 0};
0288 
0289     ch_stat0.regx.lpcm_id = (intelhaddata->aes_bits &
0290                       IEC958_AES0_NONAUDIO) >> 1;
0291     ch_stat0.regx.clk_acc = (intelhaddata->aes_bits &
0292                       IEC958_AES3_CON_CLOCK) >> 4;
0293 
0294     switch (substream->runtime->rate) {
0295     case AUD_SAMPLE_RATE_32:
0296         ch_stat0.regx.samp_freq = CH_STATUS_MAP_32KHZ;
0297         break;
0298 
0299     case AUD_SAMPLE_RATE_44_1:
0300         ch_stat0.regx.samp_freq = CH_STATUS_MAP_44KHZ;
0301         break;
0302     case AUD_SAMPLE_RATE_48:
0303         ch_stat0.regx.samp_freq = CH_STATUS_MAP_48KHZ;
0304         break;
0305     case AUD_SAMPLE_RATE_88_2:
0306         ch_stat0.regx.samp_freq = CH_STATUS_MAP_88KHZ;
0307         break;
0308     case AUD_SAMPLE_RATE_96:
0309         ch_stat0.regx.samp_freq = CH_STATUS_MAP_96KHZ;
0310         break;
0311     case AUD_SAMPLE_RATE_176_4:
0312         ch_stat0.regx.samp_freq = CH_STATUS_MAP_176KHZ;
0313         break;
0314     case AUD_SAMPLE_RATE_192:
0315         ch_stat0.regx.samp_freq = CH_STATUS_MAP_192KHZ;
0316         break;
0317 
0318     default:
0319         /* control should never come here */
0320         return -EINVAL;
0321     }
0322 
0323     had_write_register(intelhaddata,
0324                AUD_CH_STATUS_0, ch_stat0.regval);
0325 
0326     switch (substream->runtime->format) {
0327     case SNDRV_PCM_FORMAT_S16_LE:
0328         ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_20;
0329         ch_stat1.regx.wrd_len = SMPL_WIDTH_16BITS;
0330         break;
0331     case SNDRV_PCM_FORMAT_S24_LE:
0332     case SNDRV_PCM_FORMAT_S32_LE:
0333         ch_stat1.regx.max_wrd_len = MAX_SMPL_WIDTH_24;
0334         ch_stat1.regx.wrd_len = SMPL_WIDTH_24BITS;
0335         break;
0336     default:
0337         return -EINVAL;
0338     }
0339 
0340     had_write_register(intelhaddata,
0341                AUD_CH_STATUS_1, ch_stat1.regval);
0342     return 0;
0343 }
0344 
0345 /*
0346  * function to initialize audio
0347  * registers and buffer configuration registers
0348  * This function is called in the prepare callback
0349  */
0350 static int had_init_audio_ctrl(struct snd_pcm_substream *substream,
0351                    struct snd_intelhad *intelhaddata)
0352 {
0353     union aud_cfg cfg_val = {.regval = 0};
0354     union aud_buf_config buf_cfg = {.regval = 0};
0355     u8 channels;
0356 
0357     had_prog_status_reg(substream, intelhaddata);
0358 
0359     buf_cfg.regx.audio_fifo_watermark = FIFO_THRESHOLD;
0360     buf_cfg.regx.dma_fifo_watermark = DMA_FIFO_THRESHOLD;
0361     buf_cfg.regx.aud_delay = 0;
0362     had_write_register(intelhaddata, AUD_BUF_CONFIG, buf_cfg.regval);
0363 
0364     channels = substream->runtime->channels;
0365     cfg_val.regx.num_ch = channels - 2;
0366     if (channels <= 2)
0367         cfg_val.regx.layout = LAYOUT0;
0368     else
0369         cfg_val.regx.layout = LAYOUT1;
0370 
0371     if (substream->runtime->format == SNDRV_PCM_FORMAT_S16_LE)
0372         cfg_val.regx.packet_mode = 1;
0373 
0374     if (substream->runtime->format == SNDRV_PCM_FORMAT_S32_LE)
0375         cfg_val.regx.left_align = 1;
0376 
0377     cfg_val.regx.val_bit = 1;
0378 
0379     /* fix up the DP bits */
0380     if (intelhaddata->dp_output) {
0381         cfg_val.regx.dp_modei = 1;
0382         cfg_val.regx.set = 1;
0383     }
0384 
0385     had_write_register(intelhaddata, AUD_CONFIG, cfg_val.regval);
0386     intelhaddata->aud_config = cfg_val;
0387     return 0;
0388 }
0389 
0390 /*
0391  * Compute derived values in channel_allocations[].
0392  */
0393 static void init_channel_allocations(void)
0394 {
0395     int i, j;
0396     struct cea_channel_speaker_allocation *p;
0397 
0398     for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
0399         p = channel_allocations + i;
0400         p->channels = 0;
0401         p->spk_mask = 0;
0402         for (j = 0; j < ARRAY_SIZE(p->speakers); j++)
0403             if (p->speakers[j]) {
0404                 p->channels++;
0405                 p->spk_mask |= p->speakers[j];
0406             }
0407     }
0408 }
0409 
0410 /*
0411  * The transformation takes two steps:
0412  *
0413  *      eld->spk_alloc => (eld_speaker_allocation_bits[]) => spk_mask
0414  *            spk_mask => (channel_allocations[])         => ai->CA
0415  *
0416  * TODO: it could select the wrong CA from multiple candidates.
0417  */
0418 static int had_channel_allocation(struct snd_intelhad *intelhaddata,
0419                   int channels)
0420 {
0421     int i;
0422     int ca = 0;
0423     int spk_mask = 0;
0424 
0425     /*
0426      * CA defaults to 0 for basic stereo audio
0427      */
0428     if (channels <= 2)
0429         return 0;
0430 
0431     /*
0432      * expand ELD's speaker allocation mask
0433      *
0434      * ELD tells the speaker mask in a compact(paired) form,
0435      * expand ELD's notions to match the ones used by Audio InfoFrame.
0436      */
0437 
0438     for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
0439         if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
0440             spk_mask |= eld_speaker_allocation_bits[i];
0441     }
0442 
0443     /* search for the first working match in the CA table */
0444     for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
0445         if (channels == channel_allocations[i].channels &&
0446         (spk_mask & channel_allocations[i].spk_mask) ==
0447                 channel_allocations[i].spk_mask) {
0448             ca = channel_allocations[i].ca_index;
0449             break;
0450         }
0451     }
0452 
0453     dev_dbg(intelhaddata->dev, "select CA 0x%x for %d\n", ca, channels);
0454 
0455     return ca;
0456 }
0457 
0458 /* from speaker bit mask to ALSA API channel position */
0459 static int spk_to_chmap(int spk)
0460 {
0461     const struct channel_map_table *t = map_tables;
0462 
0463     for (; t->map; t++) {
0464         if (t->spk_mask == spk)
0465             return t->map;
0466     }
0467     return 0;
0468 }
0469 
0470 static void had_build_channel_allocation_map(struct snd_intelhad *intelhaddata)
0471 {
0472     int i, c;
0473     int spk_mask = 0;
0474     struct snd_pcm_chmap_elem *chmap;
0475     u8 eld_high, eld_high_mask = 0xF0;
0476     u8 high_msb;
0477 
0478     kfree(intelhaddata->chmap->chmap);
0479     intelhaddata->chmap->chmap = NULL;
0480 
0481     chmap = kzalloc(sizeof(*chmap), GFP_KERNEL);
0482     if (!chmap)
0483         return;
0484 
0485     dev_dbg(intelhaddata->dev, "eld speaker = %x\n",
0486         intelhaddata->eld[DRM_ELD_SPEAKER]);
0487 
0488     /* WA: Fix the max channel supported to 8 */
0489 
0490     /*
0491      * Sink may support more than 8 channels, if eld_high has more than
0492      * one bit set. SOC supports max 8 channels.
0493      * Refer eld_speaker_allocation_bits, for sink speaker allocation
0494      */
0495 
0496     /* if 0x2F < eld < 0x4F fall back to 0x2f, else fall back to 0x4F */
0497     eld_high = intelhaddata->eld[DRM_ELD_SPEAKER] & eld_high_mask;
0498     if ((eld_high & (eld_high-1)) && (eld_high > 0x1F)) {
0499         /* eld_high & (eld_high-1): if more than 1 bit set */
0500         /* 0x1F: 7 channels */
0501         for (i = 1; i < 4; i++) {
0502             high_msb = eld_high & (0x80 >> i);
0503             if (high_msb) {
0504                 intelhaddata->eld[DRM_ELD_SPEAKER] &=
0505                     high_msb | 0xF;
0506                 break;
0507             }
0508         }
0509     }
0510 
0511     for (i = 0; i < ARRAY_SIZE(eld_speaker_allocation_bits); i++) {
0512         if (intelhaddata->eld[DRM_ELD_SPEAKER] & (1 << i))
0513             spk_mask |= eld_speaker_allocation_bits[i];
0514     }
0515 
0516     for (i = 0; i < ARRAY_SIZE(channel_allocations); i++) {
0517         if (spk_mask == channel_allocations[i].spk_mask) {
0518             for (c = 0; c < channel_allocations[i].channels; c++) {
0519                 chmap->map[c] = spk_to_chmap(
0520                     channel_allocations[i].speakers[
0521                         (MAX_SPEAKERS - 1) - c]);
0522             }
0523             chmap->channels = channel_allocations[i].channels;
0524             intelhaddata->chmap->chmap = chmap;
0525             break;
0526         }
0527     }
0528     if (i >= ARRAY_SIZE(channel_allocations))
0529         kfree(chmap);
0530 }
0531 
0532 /*
0533  * ALSA API channel-map control callbacks
0534  */
0535 static int had_chmap_ctl_info(struct snd_kcontrol *kcontrol,
0536                 struct snd_ctl_elem_info *uinfo)
0537 {
0538     uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
0539     uinfo->count = HAD_MAX_CHANNEL;
0540     uinfo->value.integer.min = 0;
0541     uinfo->value.integer.max = SNDRV_CHMAP_LAST;
0542     return 0;
0543 }
0544 
0545 static int had_chmap_ctl_get(struct snd_kcontrol *kcontrol,
0546                 struct snd_ctl_elem_value *ucontrol)
0547 {
0548     struct snd_pcm_chmap *info = snd_kcontrol_chip(kcontrol);
0549     struct snd_intelhad *intelhaddata = info->private_data;
0550     int i;
0551     const struct snd_pcm_chmap_elem *chmap;
0552 
0553     memset(ucontrol->value.integer.value, 0,
0554            sizeof(long) * HAD_MAX_CHANNEL);
0555     mutex_lock(&intelhaddata->mutex);
0556     if (!intelhaddata->chmap->chmap) {
0557         mutex_unlock(&intelhaddata->mutex);
0558         return 0;
0559     }
0560 
0561     chmap = intelhaddata->chmap->chmap;
0562     for (i = 0; i < chmap->channels; i++)
0563         ucontrol->value.integer.value[i] = chmap->map[i];
0564     mutex_unlock(&intelhaddata->mutex);
0565 
0566     return 0;
0567 }
0568 
0569 static int had_register_chmap_ctls(struct snd_intelhad *intelhaddata,
0570                         struct snd_pcm *pcm)
0571 {
0572     int err;
0573 
0574     err = snd_pcm_add_chmap_ctls(pcm, SNDRV_PCM_STREAM_PLAYBACK,
0575             NULL, 0, (unsigned long)intelhaddata,
0576             &intelhaddata->chmap);
0577     if (err < 0)
0578         return err;
0579 
0580     intelhaddata->chmap->private_data = intelhaddata;
0581     intelhaddata->chmap->kctl->info = had_chmap_ctl_info;
0582     intelhaddata->chmap->kctl->get = had_chmap_ctl_get;
0583     intelhaddata->chmap->chmap = NULL;
0584     return 0;
0585 }
0586 
0587 /*
0588  * Initialize Data Island Packets registers
0589  * This function is called in the prepare callback
0590  */
0591 static void had_prog_dip(struct snd_pcm_substream *substream,
0592              struct snd_intelhad *intelhaddata)
0593 {
0594     int i;
0595     union aud_ctrl_st ctrl_state = {.regval = 0};
0596     union aud_info_frame2 frame2 = {.regval = 0};
0597     union aud_info_frame3 frame3 = {.regval = 0};
0598     u8 checksum = 0;
0599     u32 info_frame;
0600     int channels;
0601     int ca;
0602 
0603     channels = substream->runtime->channels;
0604 
0605     had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
0606 
0607     ca = had_channel_allocation(intelhaddata, channels);
0608     if (intelhaddata->dp_output) {
0609         info_frame = DP_INFO_FRAME_WORD1;
0610         frame2.regval = (substream->runtime->channels - 1) | (ca << 24);
0611     } else {
0612         info_frame = HDMI_INFO_FRAME_WORD1;
0613         frame2.regx.chnl_cnt = substream->runtime->channels - 1;
0614         frame3.regx.chnl_alloc = ca;
0615 
0616         /* Calculte the byte wide checksum for all valid DIP words */
0617         for (i = 0; i < BYTES_PER_WORD; i++)
0618             checksum += (info_frame >> (i * 8)) & 0xff;
0619         for (i = 0; i < BYTES_PER_WORD; i++)
0620             checksum += (frame2.regval >> (i * 8)) & 0xff;
0621         for (i = 0; i < BYTES_PER_WORD; i++)
0622             checksum += (frame3.regval >> (i * 8)) & 0xff;
0623 
0624         frame2.regx.chksum = -(checksum);
0625     }
0626 
0627     had_write_register(intelhaddata, AUD_HDMIW_INFOFR, info_frame);
0628     had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame2.regval);
0629     had_write_register(intelhaddata, AUD_HDMIW_INFOFR, frame3.regval);
0630 
0631     /* program remaining DIP words with zero */
0632     for (i = 0; i < HAD_MAX_DIP_WORDS-VALID_DIP_WORDS; i++)
0633         had_write_register(intelhaddata, AUD_HDMIW_INFOFR, 0x0);
0634 
0635     ctrl_state.regx.dip_freq = 1;
0636     ctrl_state.regx.dip_en_sta = 1;
0637     had_write_register(intelhaddata, AUD_CNTL_ST, ctrl_state.regval);
0638 }
0639 
0640 static int had_calculate_maud_value(u32 aud_samp_freq, u32 link_rate)
0641 {
0642     u32 maud_val;
0643 
0644     /* Select maud according to DP 1.2 spec */
0645     if (link_rate == DP_2_7_GHZ) {
0646         switch (aud_samp_freq) {
0647         case AUD_SAMPLE_RATE_32:
0648             maud_val = AUD_SAMPLE_RATE_32_DP_2_7_MAUD_VAL;
0649             break;
0650 
0651         case AUD_SAMPLE_RATE_44_1:
0652             maud_val = AUD_SAMPLE_RATE_44_1_DP_2_7_MAUD_VAL;
0653             break;
0654 
0655         case AUD_SAMPLE_RATE_48:
0656             maud_val = AUD_SAMPLE_RATE_48_DP_2_7_MAUD_VAL;
0657             break;
0658 
0659         case AUD_SAMPLE_RATE_88_2:
0660             maud_val = AUD_SAMPLE_RATE_88_2_DP_2_7_MAUD_VAL;
0661             break;
0662 
0663         case AUD_SAMPLE_RATE_96:
0664             maud_val = AUD_SAMPLE_RATE_96_DP_2_7_MAUD_VAL;
0665             break;
0666 
0667         case AUD_SAMPLE_RATE_176_4:
0668             maud_val = AUD_SAMPLE_RATE_176_4_DP_2_7_MAUD_VAL;
0669             break;
0670 
0671         case HAD_MAX_RATE:
0672             maud_val = HAD_MAX_RATE_DP_2_7_MAUD_VAL;
0673             break;
0674 
0675         default:
0676             maud_val = -EINVAL;
0677             break;
0678         }
0679     } else if (link_rate == DP_1_62_GHZ) {
0680         switch (aud_samp_freq) {
0681         case AUD_SAMPLE_RATE_32:
0682             maud_val = AUD_SAMPLE_RATE_32_DP_1_62_MAUD_VAL;
0683             break;
0684 
0685         case AUD_SAMPLE_RATE_44_1:
0686             maud_val = AUD_SAMPLE_RATE_44_1_DP_1_62_MAUD_VAL;
0687             break;
0688 
0689         case AUD_SAMPLE_RATE_48:
0690             maud_val = AUD_SAMPLE_RATE_48_DP_1_62_MAUD_VAL;
0691             break;
0692 
0693         case AUD_SAMPLE_RATE_88_2:
0694             maud_val = AUD_SAMPLE_RATE_88_2_DP_1_62_MAUD_VAL;
0695             break;
0696 
0697         case AUD_SAMPLE_RATE_96:
0698             maud_val = AUD_SAMPLE_RATE_96_DP_1_62_MAUD_VAL;
0699             break;
0700 
0701         case AUD_SAMPLE_RATE_176_4:
0702             maud_val = AUD_SAMPLE_RATE_176_4_DP_1_62_MAUD_VAL;
0703             break;
0704 
0705         case HAD_MAX_RATE:
0706             maud_val = HAD_MAX_RATE_DP_1_62_MAUD_VAL;
0707             break;
0708 
0709         default:
0710             maud_val = -EINVAL;
0711             break;
0712         }
0713     } else
0714         maud_val = -EINVAL;
0715 
0716     return maud_val;
0717 }
0718 
0719 /*
0720  * Program HDMI audio CTS value
0721  *
0722  * @aud_samp_freq: sampling frequency of audio data
0723  * @tmds: sampling frequency of the display data
0724  * @link_rate: DP link rate
0725  * @n_param: N value, depends on aud_samp_freq
0726  * @intelhaddata: substream private data
0727  *
0728  * Program CTS register based on the audio and display sampling frequency
0729  */
0730 static void had_prog_cts(u32 aud_samp_freq, u32 tmds, u32 link_rate,
0731              u32 n_param, struct snd_intelhad *intelhaddata)
0732 {
0733     u32 cts_val;
0734     u64 dividend, divisor;
0735 
0736     if (intelhaddata->dp_output) {
0737         /* Substitute cts_val with Maud according to DP 1.2 spec*/
0738         cts_val = had_calculate_maud_value(aud_samp_freq, link_rate);
0739     } else {
0740         /* Calculate CTS according to HDMI 1.3a spec*/
0741         dividend = (u64)tmds * n_param*1000;
0742         divisor = 128 * aud_samp_freq;
0743         cts_val = div64_u64(dividend, divisor);
0744     }
0745     dev_dbg(intelhaddata->dev, "TMDS value=%d, N value=%d, CTS Value=%d\n",
0746          tmds, n_param, cts_val);
0747     had_write_register(intelhaddata, AUD_HDMI_CTS, (BIT(24) | cts_val));
0748 }
0749 
0750 static int had_calculate_n_value(u32 aud_samp_freq)
0751 {
0752     int n_val;
0753 
0754     /* Select N according to HDMI 1.3a spec*/
0755     switch (aud_samp_freq) {
0756     case AUD_SAMPLE_RATE_32:
0757         n_val = 4096;
0758         break;
0759 
0760     case AUD_SAMPLE_RATE_44_1:
0761         n_val = 6272;
0762         break;
0763 
0764     case AUD_SAMPLE_RATE_48:
0765         n_val = 6144;
0766         break;
0767 
0768     case AUD_SAMPLE_RATE_88_2:
0769         n_val = 12544;
0770         break;
0771 
0772     case AUD_SAMPLE_RATE_96:
0773         n_val = 12288;
0774         break;
0775 
0776     case AUD_SAMPLE_RATE_176_4:
0777         n_val = 25088;
0778         break;
0779 
0780     case HAD_MAX_RATE:
0781         n_val = 24576;
0782         break;
0783 
0784     default:
0785         n_val = -EINVAL;
0786         break;
0787     }
0788     return n_val;
0789 }
0790 
0791 /*
0792  * Program HDMI audio N value
0793  *
0794  * @aud_samp_freq: sampling frequency of audio data
0795  * @n_param: N value, depends on aud_samp_freq
0796  * @intelhaddata: substream private data
0797  *
0798  * This function is called in the prepare callback.
0799  * It programs based on the audio and display sampling frequency
0800  */
0801 static int had_prog_n(u32 aud_samp_freq, u32 *n_param,
0802               struct snd_intelhad *intelhaddata)
0803 {
0804     int n_val;
0805 
0806     if (intelhaddata->dp_output) {
0807         /*
0808          * According to DP specs, Maud and Naud values hold
0809          * a relationship, which is stated as:
0810          * Maud/Naud = 512 * fs / f_LS_Clk
0811          * where, fs is the sampling frequency of the audio stream
0812          * and Naud is 32768 for Async clock.
0813          */
0814 
0815         n_val = DP_NAUD_VAL;
0816     } else
0817         n_val = had_calculate_n_value(aud_samp_freq);
0818 
0819     if (n_val < 0)
0820         return n_val;
0821 
0822     had_write_register(intelhaddata, AUD_N_ENABLE, (BIT(24) | n_val));
0823     *n_param = n_val;
0824     return 0;
0825 }
0826 
0827 /*
0828  * PCM ring buffer handling
0829  *
0830  * The hardware provides a ring buffer with the fixed 4 buffer descriptors
0831  * (BDs).  The driver maps these 4 BDs onto the PCM ring buffer.  The mapping
0832  * moves at each period elapsed.  The below illustrates how it works:
0833  *
0834  * At time=0
0835  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
0836  *  BD  | 0 | 1 | 2 | 3 |
0837  *
0838  * At time=1 (period elapsed)
0839  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
0840  *  BD      | 1 | 2 | 3 | 0 |
0841  *
0842  * At time=2 (second period elapsed)
0843  *  PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
0844  *  BD          | 2 | 3 | 0 | 1 |
0845  *
0846  * The bd_head field points to the index of the BD to be read.  It's also the
0847  * position to be filled at next.  The pcm_head and the pcm_filled fields
0848  * point to the indices of the current position and of the next position to
0849  * be filled, respectively.  For PCM buffer there are both _head and _filled
0850  * because they may be difference when nperiods > 4.  For example, in the
0851  * example above at t=1, bd_head=1 and pcm_head=1 while pcm_filled=5:
0852  *
0853  * pcm_head (=1) --v               v-- pcm_filled (=5)
0854  *       PCM | 0 | 1 | 2 | 3 | 4 | 5 | .... |n-1|
0855  *       BD      | 1 | 2 | 3 | 0 |
0856  *  bd_head (=1) --^               ^-- next to fill (= bd_head)
0857  *
0858  * For nperiods < 4, the remaining BDs out of 4 are marked as invalid, so that
0859  * the hardware skips those BDs in the loop.
0860  *
0861  * An exceptional setup is the case with nperiods=1.  Since we have to update
0862  * BDs after finishing one BD processing, we'd need at least two BDs, where
0863  * both BDs point to the same content, the same address, the same size of the
0864  * whole PCM buffer.
0865  */
0866 
0867 #define AUD_BUF_ADDR(x)     (AUD_BUF_A_ADDR + (x) * HAD_REG_WIDTH)
0868 #define AUD_BUF_LEN(x)      (AUD_BUF_A_LENGTH + (x) * HAD_REG_WIDTH)
0869 
0870 /* Set up a buffer descriptor at the "filled" position */
0871 static void had_prog_bd(struct snd_pcm_substream *substream,
0872             struct snd_intelhad *intelhaddata)
0873 {
0874     int idx = intelhaddata->bd_head;
0875     int ofs = intelhaddata->pcmbuf_filled * intelhaddata->period_bytes;
0876     u32 addr = substream->runtime->dma_addr + ofs;
0877 
0878     addr |= AUD_BUF_VALID;
0879     if (!substream->runtime->no_period_wakeup)
0880         addr |= AUD_BUF_INTR_EN;
0881     had_write_register(intelhaddata, AUD_BUF_ADDR(idx), addr);
0882     had_write_register(intelhaddata, AUD_BUF_LEN(idx),
0883                intelhaddata->period_bytes);
0884 
0885     /* advance the indices to the next */
0886     intelhaddata->bd_head++;
0887     intelhaddata->bd_head %= intelhaddata->num_bds;
0888     intelhaddata->pcmbuf_filled++;
0889     intelhaddata->pcmbuf_filled %= substream->runtime->periods;
0890 }
0891 
0892 /* invalidate a buffer descriptor with the given index */
0893 static void had_invalidate_bd(struct snd_intelhad *intelhaddata,
0894                   int idx)
0895 {
0896     had_write_register(intelhaddata, AUD_BUF_ADDR(idx), 0);
0897     had_write_register(intelhaddata, AUD_BUF_LEN(idx), 0);
0898 }
0899 
0900 /* Initial programming of ring buffer */
0901 static void had_init_ringbuf(struct snd_pcm_substream *substream,
0902                  struct snd_intelhad *intelhaddata)
0903 {
0904     struct snd_pcm_runtime *runtime = substream->runtime;
0905     int i, num_periods;
0906 
0907     num_periods = runtime->periods;
0908     intelhaddata->num_bds = min(num_periods, HAD_NUM_OF_RING_BUFS);
0909     /* set the minimum 2 BDs for num_periods=1 */
0910     intelhaddata->num_bds = max(intelhaddata->num_bds, 2U);
0911     intelhaddata->period_bytes =
0912         frames_to_bytes(runtime, runtime->period_size);
0913     WARN_ON(intelhaddata->period_bytes & 0x3f);
0914 
0915     intelhaddata->bd_head = 0;
0916     intelhaddata->pcmbuf_head = 0;
0917     intelhaddata->pcmbuf_filled = 0;
0918 
0919     for (i = 0; i < HAD_NUM_OF_RING_BUFS; i++) {
0920         if (i < intelhaddata->num_bds)
0921             had_prog_bd(substream, intelhaddata);
0922         else /* invalidate the rest */
0923             had_invalidate_bd(intelhaddata, i);
0924     }
0925 
0926     intelhaddata->bd_head = 0; /* reset at head again before starting */
0927 }
0928 
0929 /* process a bd, advance to the next */
0930 static void had_advance_ringbuf(struct snd_pcm_substream *substream,
0931                 struct snd_intelhad *intelhaddata)
0932 {
0933     int num_periods = substream->runtime->periods;
0934 
0935     /* reprogram the next buffer */
0936     had_prog_bd(substream, intelhaddata);
0937 
0938     /* proceed to next */
0939     intelhaddata->pcmbuf_head++;
0940     intelhaddata->pcmbuf_head %= num_periods;
0941 }
0942 
0943 /* process the current BD(s);
0944  * returns the current PCM buffer byte position, or -EPIPE for underrun.
0945  */
0946 static int had_process_ringbuf(struct snd_pcm_substream *substream,
0947                    struct snd_intelhad *intelhaddata)
0948 {
0949     int len, processed;
0950     unsigned long flags;
0951 
0952     processed = 0;
0953     spin_lock_irqsave(&intelhaddata->had_spinlock, flags);
0954     for (;;) {
0955         /* get the remaining bytes on the buffer */
0956         had_read_register(intelhaddata,
0957                   AUD_BUF_LEN(intelhaddata->bd_head),
0958                   &len);
0959         if (len < 0 || len > intelhaddata->period_bytes) {
0960             dev_dbg(intelhaddata->dev, "Invalid buf length %d\n",
0961                 len);
0962             len = -EPIPE;
0963             goto out;
0964         }
0965 
0966         if (len > 0) /* OK, this is the current buffer */
0967             break;
0968 
0969         /* len=0 => already empty, check the next buffer */
0970         if (++processed >= intelhaddata->num_bds) {
0971             len = -EPIPE; /* all empty? - report underrun */
0972             goto out;
0973         }
0974         had_advance_ringbuf(substream, intelhaddata);
0975     }
0976 
0977     len = intelhaddata->period_bytes - len;
0978     len += intelhaddata->period_bytes * intelhaddata->pcmbuf_head;
0979  out:
0980     spin_unlock_irqrestore(&intelhaddata->had_spinlock, flags);
0981     return len;
0982 }
0983 
0984 /* called from irq handler */
0985 static void had_process_buffer_done(struct snd_intelhad *intelhaddata)
0986 {
0987     struct snd_pcm_substream *substream;
0988 
0989     substream = had_substream_get(intelhaddata);
0990     if (!substream)
0991         return; /* no stream? - bail out */
0992 
0993     if (!intelhaddata->connected) {
0994         snd_pcm_stop_xrun(substream);
0995         goto out; /* disconnected? - bail out */
0996     }
0997 
0998     /* process or stop the stream */
0999     if (had_process_ringbuf(substream, intelhaddata) < 0)
1000         snd_pcm_stop_xrun(substream);
1001     else
1002         snd_pcm_period_elapsed(substream);
1003 
1004  out:
1005     had_substream_put(intelhaddata);
1006 }
1007 
1008 /*
1009  * The interrupt status 'sticky' bits might not be cleared by
1010  * setting '1' to that bit once...
1011  */
1012 static void wait_clear_underrun_bit(struct snd_intelhad *intelhaddata)
1013 {
1014     int i;
1015     u32 val;
1016 
1017     for (i = 0; i < 100; i++) {
1018         /* clear bit30, 31 AUD_HDMI_STATUS */
1019         had_read_register(intelhaddata, AUD_HDMI_STATUS, &val);
1020         if (!(val & AUD_HDMI_STATUS_MASK_UNDERRUN))
1021             return;
1022         udelay(100);
1023         cond_resched();
1024         had_write_register(intelhaddata, AUD_HDMI_STATUS, val);
1025     }
1026     dev_err(intelhaddata->dev, "Unable to clear UNDERRUN bits\n");
1027 }
1028 
1029 /* Perform some reset procedure after stopping the stream;
1030  * this is called from prepare or hw_free callbacks once after trigger STOP
1031  * or underrun has been processed in order to settle down the h/w state.
1032  */
1033 static int had_pcm_sync_stop(struct snd_pcm_substream *substream)
1034 {
1035     struct snd_intelhad *intelhaddata = snd_pcm_substream_chip(substream);
1036 
1037     if (!intelhaddata->connected)
1038         return 0;
1039 
1040     /* Reset buffer pointers */
1041     had_reset_audio(intelhaddata);
1042     wait_clear_underrun_bit(intelhaddata);
1043     return 0;
1044 }
1045 
1046 /* called from irq handler */
1047 static void had_process_buffer_underrun(struct snd_intelhad *intelhaddata)
1048 {
1049     struct snd_pcm_substream *substream;
1050 
1051     /* Report UNDERRUN error to above layers */
1052     substream = had_substream_get(intelhaddata);
1053     if (substream) {
1054         snd_pcm_stop_xrun(substream);
1055         had_substream_put(intelhaddata);
1056     }
1057 }
1058 
1059 /*
1060  * ALSA PCM open callback
1061  */
1062 static int had_pcm_open(struct snd_pcm_substream *substream)
1063 {
1064     struct snd_intelhad *intelhaddata;
1065     struct snd_pcm_runtime *runtime;
1066     int retval;
1067 
1068     intelhaddata = snd_pcm_substream_chip(substream);
1069     runtime = substream->runtime;
1070 
1071     retval = pm_runtime_resume_and_get(intelhaddata->dev);
1072     if (retval < 0)
1073         return retval;
1074 
1075     /* set the runtime hw parameter with local snd_pcm_hardware struct */
1076     runtime->hw = had_pcm_hardware;
1077 
1078     retval = snd_pcm_hw_constraint_integer(runtime,
1079              SNDRV_PCM_HW_PARAM_PERIODS);
1080     if (retval < 0)
1081         goto error;
1082 
1083     /* Make sure, that the period size is always aligned
1084      * 64byte boundary
1085      */
1086     retval = snd_pcm_hw_constraint_step(substream->runtime, 0,
1087             SNDRV_PCM_HW_PARAM_PERIOD_BYTES, 64);
1088     if (retval < 0)
1089         goto error;
1090 
1091     retval = snd_pcm_hw_constraint_msbits(runtime, 0, 32, 24);
1092     if (retval < 0)
1093         goto error;
1094 
1095     /* expose PCM substream */
1096     spin_lock_irq(&intelhaddata->had_spinlock);
1097     intelhaddata->stream_info.substream = substream;
1098     intelhaddata->stream_info.substream_refcount++;
1099     spin_unlock_irq(&intelhaddata->had_spinlock);
1100 
1101     return retval;
1102  error:
1103     pm_runtime_mark_last_busy(intelhaddata->dev);
1104     pm_runtime_put_autosuspend(intelhaddata->dev);
1105     return retval;
1106 }
1107 
1108 /*
1109  * ALSA PCM close callback
1110  */
1111 static int had_pcm_close(struct snd_pcm_substream *substream)
1112 {
1113     struct snd_intelhad *intelhaddata;
1114 
1115     intelhaddata = snd_pcm_substream_chip(substream);
1116 
1117     /* unreference and sync with the pending PCM accesses */
1118     spin_lock_irq(&intelhaddata->had_spinlock);
1119     intelhaddata->stream_info.substream = NULL;
1120     intelhaddata->stream_info.substream_refcount--;
1121     while (intelhaddata->stream_info.substream_refcount > 0) {
1122         spin_unlock_irq(&intelhaddata->had_spinlock);
1123         cpu_relax();
1124         spin_lock_irq(&intelhaddata->had_spinlock);
1125     }
1126     spin_unlock_irq(&intelhaddata->had_spinlock);
1127 
1128     pm_runtime_mark_last_busy(intelhaddata->dev);
1129     pm_runtime_put_autosuspend(intelhaddata->dev);
1130     return 0;
1131 }
1132 
1133 /*
1134  * ALSA PCM hw_params callback
1135  */
1136 static int had_pcm_hw_params(struct snd_pcm_substream *substream,
1137                  struct snd_pcm_hw_params *hw_params)
1138 {
1139     struct snd_intelhad *intelhaddata;
1140     int buf_size;
1141 
1142     intelhaddata = snd_pcm_substream_chip(substream);
1143     buf_size = params_buffer_bytes(hw_params);
1144     dev_dbg(intelhaddata->dev, "%s:allocated memory = %d\n",
1145         __func__, buf_size);
1146     return 0;
1147 }
1148 
1149 /*
1150  * ALSA PCM trigger callback
1151  */
1152 static int had_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1153 {
1154     int retval = 0;
1155     struct snd_intelhad *intelhaddata;
1156 
1157     intelhaddata = snd_pcm_substream_chip(substream);
1158 
1159     spin_lock(&intelhaddata->had_spinlock);
1160     switch (cmd) {
1161     case SNDRV_PCM_TRIGGER_START:
1162     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1163     case SNDRV_PCM_TRIGGER_RESUME:
1164         /* Enable Audio */
1165         had_ack_irqs(intelhaddata); /* FIXME: do we need this? */
1166         had_enable_audio(intelhaddata, true);
1167         break;
1168 
1169     case SNDRV_PCM_TRIGGER_STOP:
1170     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1171         /* Disable Audio */
1172         had_enable_audio(intelhaddata, false);
1173         break;
1174 
1175     default:
1176         retval = -EINVAL;
1177     }
1178     spin_unlock(&intelhaddata->had_spinlock);
1179     return retval;
1180 }
1181 
1182 /*
1183  * ALSA PCM prepare callback
1184  */
1185 static int had_pcm_prepare(struct snd_pcm_substream *substream)
1186 {
1187     int retval;
1188     u32 disp_samp_freq, n_param;
1189     u32 link_rate = 0;
1190     struct snd_intelhad *intelhaddata;
1191     struct snd_pcm_runtime *runtime;
1192 
1193     intelhaddata = snd_pcm_substream_chip(substream);
1194     runtime = substream->runtime;
1195 
1196     dev_dbg(intelhaddata->dev, "period_size=%d\n",
1197         (int)frames_to_bytes(runtime, runtime->period_size));
1198     dev_dbg(intelhaddata->dev, "periods=%d\n", runtime->periods);
1199     dev_dbg(intelhaddata->dev, "buffer_size=%d\n",
1200         (int)snd_pcm_lib_buffer_bytes(substream));
1201     dev_dbg(intelhaddata->dev, "rate=%d\n", runtime->rate);
1202     dev_dbg(intelhaddata->dev, "channels=%d\n", runtime->channels);
1203 
1204     /* Get N value in KHz */
1205     disp_samp_freq = intelhaddata->tmds_clock_speed;
1206 
1207     retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1208     if (retval) {
1209         dev_err(intelhaddata->dev,
1210             "programming N value failed %#x\n", retval);
1211         goto prep_end;
1212     }
1213 
1214     if (intelhaddata->dp_output)
1215         link_rate = intelhaddata->link_rate;
1216 
1217     had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1218              n_param, intelhaddata);
1219 
1220     had_prog_dip(substream, intelhaddata);
1221 
1222     retval = had_init_audio_ctrl(substream, intelhaddata);
1223 
1224     /* Prog buffer address */
1225     had_init_ringbuf(substream, intelhaddata);
1226 
1227     /*
1228      * Program channel mapping in following order:
1229      * FL, FR, C, LFE, RL, RR
1230      */
1231 
1232     had_write_register(intelhaddata, AUD_BUF_CH_SWAP, SWAP_LFE_CENTER);
1233 
1234 prep_end:
1235     return retval;
1236 }
1237 
1238 /*
1239  * ALSA PCM pointer callback
1240  */
1241 static snd_pcm_uframes_t had_pcm_pointer(struct snd_pcm_substream *substream)
1242 {
1243     struct snd_intelhad *intelhaddata;
1244     int len;
1245 
1246     intelhaddata = snd_pcm_substream_chip(substream);
1247 
1248     if (!intelhaddata->connected)
1249         return SNDRV_PCM_POS_XRUN;
1250 
1251     len = had_process_ringbuf(substream, intelhaddata);
1252     if (len < 0)
1253         return SNDRV_PCM_POS_XRUN;
1254     len = bytes_to_frames(substream->runtime, len);
1255     /* wrapping may happen when periods=1 */
1256     len %= substream->runtime->buffer_size;
1257     return len;
1258 }
1259 
1260 /*
1261  * ALSA PCM ops
1262  */
1263 static const struct snd_pcm_ops had_pcm_ops = {
1264     .open =     had_pcm_open,
1265     .close =    had_pcm_close,
1266     .hw_params =    had_pcm_hw_params,
1267     .prepare =  had_pcm_prepare,
1268     .trigger =  had_pcm_trigger,
1269     .sync_stop =    had_pcm_sync_stop,
1270     .pointer =  had_pcm_pointer,
1271 };
1272 
1273 /* process mode change of the running stream; called in mutex */
1274 static int had_process_mode_change(struct snd_intelhad *intelhaddata)
1275 {
1276     struct snd_pcm_substream *substream;
1277     int retval = 0;
1278     u32 disp_samp_freq, n_param;
1279     u32 link_rate = 0;
1280 
1281     substream = had_substream_get(intelhaddata);
1282     if (!substream)
1283         return 0;
1284 
1285     /* Disable Audio */
1286     had_enable_audio(intelhaddata, false);
1287 
1288     /* Update CTS value */
1289     disp_samp_freq = intelhaddata->tmds_clock_speed;
1290 
1291     retval = had_prog_n(substream->runtime->rate, &n_param, intelhaddata);
1292     if (retval) {
1293         dev_err(intelhaddata->dev,
1294             "programming N value failed %#x\n", retval);
1295         goto out;
1296     }
1297 
1298     if (intelhaddata->dp_output)
1299         link_rate = intelhaddata->link_rate;
1300 
1301     had_prog_cts(substream->runtime->rate, disp_samp_freq, link_rate,
1302              n_param, intelhaddata);
1303 
1304     /* Enable Audio */
1305     had_enable_audio(intelhaddata, true);
1306 
1307 out:
1308     had_substream_put(intelhaddata);
1309     return retval;
1310 }
1311 
1312 /* process hot plug, called from wq with mutex locked */
1313 static void had_process_hot_plug(struct snd_intelhad *intelhaddata)
1314 {
1315     struct snd_pcm_substream *substream;
1316 
1317     spin_lock_irq(&intelhaddata->had_spinlock);
1318     if (intelhaddata->connected) {
1319         dev_dbg(intelhaddata->dev, "Device already connected\n");
1320         spin_unlock_irq(&intelhaddata->had_spinlock);
1321         return;
1322     }
1323 
1324     /* Disable Audio */
1325     had_enable_audio(intelhaddata, false);
1326 
1327     intelhaddata->connected = true;
1328     dev_dbg(intelhaddata->dev,
1329         "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_CONNECTED\n",
1330             __func__, __LINE__);
1331     spin_unlock_irq(&intelhaddata->had_spinlock);
1332 
1333     had_build_channel_allocation_map(intelhaddata);
1334 
1335     /* Report to above ALSA layer */
1336     substream = had_substream_get(intelhaddata);
1337     if (substream) {
1338         snd_pcm_stop_xrun(substream);
1339         had_substream_put(intelhaddata);
1340     }
1341 
1342     snd_jack_report(intelhaddata->jack, SND_JACK_AVOUT);
1343 }
1344 
1345 /* process hot unplug, called from wq with mutex locked */
1346 static void had_process_hot_unplug(struct snd_intelhad *intelhaddata)
1347 {
1348     struct snd_pcm_substream *substream;
1349 
1350     spin_lock_irq(&intelhaddata->had_spinlock);
1351     if (!intelhaddata->connected) {
1352         dev_dbg(intelhaddata->dev, "Device already disconnected\n");
1353         spin_unlock_irq(&intelhaddata->had_spinlock);
1354         return;
1355 
1356     }
1357 
1358     /* Disable Audio */
1359     had_enable_audio(intelhaddata, false);
1360 
1361     intelhaddata->connected = false;
1362     dev_dbg(intelhaddata->dev,
1363         "%s @ %d:DEBUG PLUG/UNPLUG : HAD_DRV_DISCONNECTED\n",
1364             __func__, __LINE__);
1365     spin_unlock_irq(&intelhaddata->had_spinlock);
1366 
1367     kfree(intelhaddata->chmap->chmap);
1368     intelhaddata->chmap->chmap = NULL;
1369 
1370     /* Report to above ALSA layer */
1371     substream = had_substream_get(intelhaddata);
1372     if (substream) {
1373         snd_pcm_stop_xrun(substream);
1374         had_substream_put(intelhaddata);
1375     }
1376 
1377     snd_jack_report(intelhaddata->jack, 0);
1378 }
1379 
1380 /*
1381  * ALSA iec958 and ELD controls
1382  */
1383 
1384 static int had_iec958_info(struct snd_kcontrol *kcontrol,
1385                 struct snd_ctl_elem_info *uinfo)
1386 {
1387     uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
1388     uinfo->count = 1;
1389     return 0;
1390 }
1391 
1392 static int had_iec958_get(struct snd_kcontrol *kcontrol,
1393                 struct snd_ctl_elem_value *ucontrol)
1394 {
1395     struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1396 
1397     mutex_lock(&intelhaddata->mutex);
1398     ucontrol->value.iec958.status[0] = (intelhaddata->aes_bits >> 0) & 0xff;
1399     ucontrol->value.iec958.status[1] = (intelhaddata->aes_bits >> 8) & 0xff;
1400     ucontrol->value.iec958.status[2] =
1401                     (intelhaddata->aes_bits >> 16) & 0xff;
1402     ucontrol->value.iec958.status[3] =
1403                     (intelhaddata->aes_bits >> 24) & 0xff;
1404     mutex_unlock(&intelhaddata->mutex);
1405     return 0;
1406 }
1407 
1408 static int had_iec958_mask_get(struct snd_kcontrol *kcontrol,
1409                 struct snd_ctl_elem_value *ucontrol)
1410 {
1411     ucontrol->value.iec958.status[0] = 0xff;
1412     ucontrol->value.iec958.status[1] = 0xff;
1413     ucontrol->value.iec958.status[2] = 0xff;
1414     ucontrol->value.iec958.status[3] = 0xff;
1415     return 0;
1416 }
1417 
1418 static int had_iec958_put(struct snd_kcontrol *kcontrol,
1419                 struct snd_ctl_elem_value *ucontrol)
1420 {
1421     unsigned int val;
1422     struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1423     int changed = 0;
1424 
1425     val = (ucontrol->value.iec958.status[0] << 0) |
1426         (ucontrol->value.iec958.status[1] << 8) |
1427         (ucontrol->value.iec958.status[2] << 16) |
1428         (ucontrol->value.iec958.status[3] << 24);
1429     mutex_lock(&intelhaddata->mutex);
1430     if (intelhaddata->aes_bits != val) {
1431         intelhaddata->aes_bits = val;
1432         changed = 1;
1433     }
1434     mutex_unlock(&intelhaddata->mutex);
1435     return changed;
1436 }
1437 
1438 static int had_ctl_eld_info(struct snd_kcontrol *kcontrol,
1439                 struct snd_ctl_elem_info *uinfo)
1440 {
1441     uinfo->type = SNDRV_CTL_ELEM_TYPE_BYTES;
1442     uinfo->count = HDMI_MAX_ELD_BYTES;
1443     return 0;
1444 }
1445 
1446 static int had_ctl_eld_get(struct snd_kcontrol *kcontrol,
1447                struct snd_ctl_elem_value *ucontrol)
1448 {
1449     struct snd_intelhad *intelhaddata = snd_kcontrol_chip(kcontrol);
1450 
1451     mutex_lock(&intelhaddata->mutex);
1452     memcpy(ucontrol->value.bytes.data, intelhaddata->eld,
1453            HDMI_MAX_ELD_BYTES);
1454     mutex_unlock(&intelhaddata->mutex);
1455     return 0;
1456 }
1457 
1458 static const struct snd_kcontrol_new had_controls[] = {
1459     {
1460         .access = SNDRV_CTL_ELEM_ACCESS_READ,
1461         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1462         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, MASK),
1463         .info = had_iec958_info, /* shared */
1464         .get = had_iec958_mask_get,
1465     },
1466     {
1467         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1468         .name = SNDRV_CTL_NAME_IEC958("", PLAYBACK, DEFAULT),
1469         .info = had_iec958_info,
1470         .get = had_iec958_get,
1471         .put = had_iec958_put,
1472     },
1473     {
1474         .access = (SNDRV_CTL_ELEM_ACCESS_READ |
1475                SNDRV_CTL_ELEM_ACCESS_VOLATILE),
1476         .iface = SNDRV_CTL_ELEM_IFACE_PCM,
1477         .name = "ELD",
1478         .info = had_ctl_eld_info,
1479         .get = had_ctl_eld_get,
1480     },
1481 };
1482 
1483 /*
1484  * audio interrupt handler
1485  */
1486 static irqreturn_t display_pipe_interrupt_handler(int irq, void *dev_id)
1487 {
1488     struct snd_intelhad_card *card_ctx = dev_id;
1489     u32 audio_stat[3] = {};
1490     int pipe, port;
1491 
1492     for_each_pipe(card_ctx, pipe) {
1493         /* use raw register access to ack IRQs even while disconnected */
1494         audio_stat[pipe] = had_read_register_raw(card_ctx, pipe,
1495                              AUD_HDMI_STATUS) &
1496             (HDMI_AUDIO_UNDERRUN | HDMI_AUDIO_BUFFER_DONE);
1497 
1498         if (audio_stat[pipe])
1499             had_write_register_raw(card_ctx, pipe,
1500                            AUD_HDMI_STATUS, audio_stat[pipe]);
1501     }
1502 
1503     for_each_port(card_ctx, port) {
1504         struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1505         int pipe = ctx->pipe;
1506 
1507         if (pipe < 0)
1508             continue;
1509 
1510         if (audio_stat[pipe] & HDMI_AUDIO_BUFFER_DONE)
1511             had_process_buffer_done(ctx);
1512         if (audio_stat[pipe] & HDMI_AUDIO_UNDERRUN)
1513             had_process_buffer_underrun(ctx);
1514     }
1515 
1516     return IRQ_HANDLED;
1517 }
1518 
1519 /*
1520  * monitor plug/unplug notification from i915; just kick off the work
1521  */
1522 static void notify_audio_lpe(struct platform_device *pdev, int port)
1523 {
1524     struct snd_intelhad_card *card_ctx = platform_get_drvdata(pdev);
1525     struct snd_intelhad *ctx;
1526 
1527     ctx = &card_ctx->pcm_ctx[single_port ? 0 : port];
1528     if (single_port)
1529         ctx->port = port;
1530 
1531     schedule_work(&ctx->hdmi_audio_wq);
1532 }
1533 
1534 /* the work to handle monitor hot plug/unplug */
1535 static void had_audio_wq(struct work_struct *work)
1536 {
1537     struct snd_intelhad *ctx =
1538         container_of(work, struct snd_intelhad, hdmi_audio_wq);
1539     struct intel_hdmi_lpe_audio_pdata *pdata = ctx->dev->platform_data;
1540     struct intel_hdmi_lpe_audio_port_pdata *ppdata = &pdata->port[ctx->port];
1541     int ret;
1542 
1543     ret = pm_runtime_resume_and_get(ctx->dev);
1544     if (ret < 0)
1545         return;
1546 
1547     mutex_lock(&ctx->mutex);
1548     if (ppdata->pipe < 0) {
1549         dev_dbg(ctx->dev, "%s: Event: HAD_NOTIFY_HOT_UNPLUG : port = %d\n",
1550             __func__, ctx->port);
1551 
1552         memset(ctx->eld, 0, sizeof(ctx->eld)); /* clear the old ELD */
1553 
1554         ctx->dp_output = false;
1555         ctx->tmds_clock_speed = 0;
1556         ctx->link_rate = 0;
1557 
1558         /* Shut down the stream */
1559         had_process_hot_unplug(ctx);
1560 
1561         ctx->pipe = -1;
1562     } else {
1563         dev_dbg(ctx->dev, "%s: HAD_NOTIFY_ELD : port = %d, tmds = %d\n",
1564             __func__, ctx->port, ppdata->ls_clock);
1565 
1566         memcpy(ctx->eld, ppdata->eld, sizeof(ctx->eld));
1567 
1568         ctx->dp_output = ppdata->dp_output;
1569         if (ctx->dp_output) {
1570             ctx->tmds_clock_speed = 0;
1571             ctx->link_rate = ppdata->ls_clock;
1572         } else {
1573             ctx->tmds_clock_speed = ppdata->ls_clock;
1574             ctx->link_rate = 0;
1575         }
1576 
1577         /*
1578          * Shut down the stream before we change
1579          * the pipe assignment for this pcm device
1580          */
1581         had_process_hot_plug(ctx);
1582 
1583         ctx->pipe = ppdata->pipe;
1584 
1585         /* Restart the stream if necessary */
1586         had_process_mode_change(ctx);
1587     }
1588 
1589     mutex_unlock(&ctx->mutex);
1590     pm_runtime_mark_last_busy(ctx->dev);
1591     pm_runtime_put_autosuspend(ctx->dev);
1592 }
1593 
1594 /*
1595  * Jack interface
1596  */
1597 static int had_create_jack(struct snd_intelhad *ctx,
1598                struct snd_pcm *pcm)
1599 {
1600     char hdmi_str[32];
1601     int err;
1602 
1603     snprintf(hdmi_str, sizeof(hdmi_str),
1604          "HDMI/DP,pcm=%d", pcm->device);
1605 
1606     err = snd_jack_new(ctx->card_ctx->card, hdmi_str,
1607                SND_JACK_AVOUT, &ctx->jack,
1608                true, false);
1609     if (err < 0)
1610         return err;
1611     ctx->jack->private_data = ctx;
1612     return 0;
1613 }
1614 
1615 /*
1616  * PM callbacks
1617  */
1618 
1619 static int __maybe_unused hdmi_lpe_audio_suspend(struct device *dev)
1620 {
1621     struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1622 
1623     snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D3hot);
1624 
1625     return 0;
1626 }
1627 
1628 static int __maybe_unused hdmi_lpe_audio_resume(struct device *dev)
1629 {
1630     struct snd_intelhad_card *card_ctx = dev_get_drvdata(dev);
1631 
1632     pm_runtime_mark_last_busy(dev);
1633 
1634     snd_power_change_state(card_ctx->card, SNDRV_CTL_POWER_D0);
1635 
1636     return 0;
1637 }
1638 
1639 /* release resources */
1640 static void hdmi_lpe_audio_free(struct snd_card *card)
1641 {
1642     struct snd_intelhad_card *card_ctx = card->private_data;
1643     struct intel_hdmi_lpe_audio_pdata *pdata = card_ctx->dev->platform_data;
1644     int port;
1645 
1646     spin_lock_irq(&pdata->lpe_audio_slock);
1647     pdata->notify_audio_lpe = NULL;
1648     spin_unlock_irq(&pdata->lpe_audio_slock);
1649 
1650     for_each_port(card_ctx, port) {
1651         struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1652 
1653         cancel_work_sync(&ctx->hdmi_audio_wq);
1654     }
1655 }
1656 
1657 /*
1658  * hdmi_lpe_audio_probe - start bridge with i915
1659  *
1660  * This function is called when the i915 driver creates the
1661  * hdmi-lpe-audio platform device.
1662  */
1663 static int __hdmi_lpe_audio_probe(struct platform_device *pdev)
1664 {
1665     struct snd_card *card;
1666     struct snd_intelhad_card *card_ctx;
1667     struct snd_intelhad *ctx;
1668     struct snd_pcm *pcm;
1669     struct intel_hdmi_lpe_audio_pdata *pdata;
1670     int irq;
1671     struct resource *res_mmio;
1672     int port, ret;
1673 
1674     pdata = pdev->dev.platform_data;
1675     if (!pdata) {
1676         dev_err(&pdev->dev, "%s: quit: pdata not allocated by i915!!\n", __func__);
1677         return -EINVAL;
1678     }
1679 
1680     /* get resources */
1681     irq = platform_get_irq(pdev, 0);
1682     if (irq < 0)
1683         return irq;
1684 
1685     res_mmio = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1686     if (!res_mmio) {
1687         dev_err(&pdev->dev, "Could not get IO_MEM resources\n");
1688         return -ENXIO;
1689     }
1690 
1691     /* create a card instance with ALSA framework */
1692     ret = snd_devm_card_new(&pdev->dev, hdmi_card_index, hdmi_card_id,
1693                 THIS_MODULE, sizeof(*card_ctx), &card);
1694     if (ret)
1695         return ret;
1696 
1697     card_ctx = card->private_data;
1698     card_ctx->dev = &pdev->dev;
1699     card_ctx->card = card;
1700     strcpy(card->driver, INTEL_HAD);
1701     strcpy(card->shortname, "Intel HDMI/DP LPE Audio");
1702     strcpy(card->longname, "Intel HDMI/DP LPE Audio");
1703 
1704     card_ctx->irq = -1;
1705 
1706     card->private_free = hdmi_lpe_audio_free;
1707 
1708     platform_set_drvdata(pdev, card_ctx);
1709 
1710     card_ctx->num_pipes = pdata->num_pipes;
1711     card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1712 
1713     for_each_port(card_ctx, port) {
1714         ctx = &card_ctx->pcm_ctx[port];
1715         ctx->card_ctx = card_ctx;
1716         ctx->dev = card_ctx->dev;
1717         ctx->port = single_port ? -1 : port;
1718         ctx->pipe = -1;
1719 
1720         spin_lock_init(&ctx->had_spinlock);
1721         mutex_init(&ctx->mutex);
1722         INIT_WORK(&ctx->hdmi_audio_wq, had_audio_wq);
1723     }
1724 
1725     dev_dbg(&pdev->dev, "%s: mmio_start = 0x%x, mmio_end = 0x%x\n",
1726         __func__, (unsigned int)res_mmio->start,
1727         (unsigned int)res_mmio->end);
1728 
1729     card_ctx->mmio_start =
1730         devm_ioremap(&pdev->dev, res_mmio->start,
1731                  (size_t)(resource_size(res_mmio)));
1732     if (!card_ctx->mmio_start) {
1733         dev_err(&pdev->dev, "Could not get ioremap\n");
1734         return -EACCES;
1735     }
1736 
1737     /* setup interrupt handler */
1738     ret = devm_request_irq(&pdev->dev, irq, display_pipe_interrupt_handler,
1739                    0, pdev->name, card_ctx);
1740     if (ret < 0) {
1741         dev_err(&pdev->dev, "request_irq failed\n");
1742         return ret;
1743     }
1744 
1745     card_ctx->irq = irq;
1746 
1747     /* only 32bit addressable */
1748     ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1749     if (ret)
1750         return ret;
1751 
1752     init_channel_allocations();
1753 
1754     card_ctx->num_pipes = pdata->num_pipes;
1755     card_ctx->num_ports = single_port ? 1 : pdata->num_ports;
1756 
1757     for_each_port(card_ctx, port) {
1758         int i;
1759 
1760         ctx = &card_ctx->pcm_ctx[port];
1761         ret = snd_pcm_new(card, INTEL_HAD, port, MAX_PB_STREAMS,
1762                   MAX_CAP_STREAMS, &pcm);
1763         if (ret)
1764             return ret;
1765 
1766         /* setup private data which can be retrieved when required */
1767         pcm->private_data = ctx;
1768         pcm->info_flags = 0;
1769         strscpy(pcm->name, card->shortname, strlen(card->shortname));
1770         /* setup the ops for playback */
1771         snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &had_pcm_ops);
1772 
1773         /* allocate dma pages;
1774          * try to allocate 600k buffer as default which is large enough
1775          */
1776         snd_pcm_set_managed_buffer_all(pcm, SNDRV_DMA_TYPE_DEV_WC,
1777                            card->dev, HAD_DEFAULT_BUFFER,
1778                            HAD_MAX_BUFFER);
1779 
1780         /* create controls */
1781         for (i = 0; i < ARRAY_SIZE(had_controls); i++) {
1782             struct snd_kcontrol *kctl;
1783 
1784             kctl = snd_ctl_new1(&had_controls[i], ctx);
1785             if (!kctl)
1786                 return -ENOMEM;
1787 
1788             kctl->id.device = pcm->device;
1789 
1790             ret = snd_ctl_add(card, kctl);
1791             if (ret < 0)
1792                 return ret;
1793         }
1794 
1795         /* Register channel map controls */
1796         ret = had_register_chmap_ctls(ctx, pcm);
1797         if (ret < 0)
1798             return ret;
1799 
1800         ret = had_create_jack(ctx, pcm);
1801         if (ret < 0)
1802             return ret;
1803     }
1804 
1805     ret = snd_card_register(card);
1806     if (ret)
1807         return ret;
1808 
1809     spin_lock_irq(&pdata->lpe_audio_slock);
1810     pdata->notify_audio_lpe = notify_audio_lpe;
1811     spin_unlock_irq(&pdata->lpe_audio_slock);
1812 
1813     pm_runtime_set_autosuspend_delay(&pdev->dev, INTEL_HDMI_AUDIO_SUSPEND_DELAY_MS);
1814     pm_runtime_use_autosuspend(&pdev->dev);
1815     pm_runtime_enable(&pdev->dev);
1816     pm_runtime_mark_last_busy(&pdev->dev);
1817     pm_runtime_idle(&pdev->dev);
1818 
1819     dev_dbg(&pdev->dev, "%s: handle pending notification\n", __func__);
1820     for_each_port(card_ctx, port) {
1821         struct snd_intelhad *ctx = &card_ctx->pcm_ctx[port];
1822 
1823         schedule_work(&ctx->hdmi_audio_wq);
1824     }
1825 
1826     return 0;
1827 }
1828 
1829 static int hdmi_lpe_audio_probe(struct platform_device *pdev)
1830 {
1831     return snd_card_free_on_error(&pdev->dev, __hdmi_lpe_audio_probe(pdev));
1832 }
1833 
1834 static const struct dev_pm_ops hdmi_lpe_audio_pm = {
1835     SET_SYSTEM_SLEEP_PM_OPS(hdmi_lpe_audio_suspend, hdmi_lpe_audio_resume)
1836 };
1837 
1838 static struct platform_driver hdmi_lpe_audio_driver = {
1839     .driver     = {
1840         .name  = "hdmi-lpe-audio",
1841         .pm = &hdmi_lpe_audio_pm,
1842     },
1843     .probe          = hdmi_lpe_audio_probe,
1844 };
1845 
1846 module_platform_driver(hdmi_lpe_audio_driver);
1847 MODULE_ALIAS("platform:hdmi_lpe_audio");
1848 
1849 MODULE_AUTHOR("Sailaja Bandarupalli <sailaja.bandarupalli@intel.com>");
1850 MODULE_AUTHOR("Ramesh Babu K V <ramesh.babu@intel.com>");
1851 MODULE_AUTHOR("Vaibhav Agarwal <vaibhav.agarwal@intel.com>");
1852 MODULE_AUTHOR("Jerome Anand <jerome.anand@intel.com>");
1853 MODULE_DESCRIPTION("Intel HDMI Audio driver");
1854 MODULE_LICENSE("GPL v2");
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