soc/xilinx/xlnx_i2s.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 //
0003 // Xilinx ASoC I2S audio support
0004 //
0005 // Copyright (C) 2018 Xilinx, Inc.
0006 //
0007 // Author: Praveen Vuppala <praveenv@xilinx.com>
0008 // Author: Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>
0009
0010 #include <linux/io.h>
0011 #include <linux/module.h>
0012 #include <linux/of.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/platform_device.h>
0015 #include <sound/pcm_params.h>
0016 #include <sound/soc.h>
0017
0018 #define DRV_NAME "xlnx_i2s"
0019
0020 #define I2S_CORE_CTRL_OFFSET        0x08
0021 #define I2S_CORE_CTRL_32BIT_LRCLK   BIT(3)
0022 #define I2S_CORE_CTRL_ENABLE        BIT(0)
0023 #define I2S_I2STIM_OFFSET       0x20
0024 #define I2S_CH0_OFFSET          0x30
0025 #define I2S_I2STIM_VALID_MASK       GENMASK(7, 0)
0026
0027 struct xlnx_i2s_drv_data {
0028     struct snd_soc_dai_driver dai_drv;
0029     void __iomem *base;
0030     unsigned int sysclk;
0031     u32 data_width;
0032     u32 channels;
0033     bool is_32bit_lrclk;
0034     struct snd_ratnum ratnum;
0035     struct snd_pcm_hw_constraint_ratnums rate_constraints;
0036 };
0037
0038 static int xlnx_i2s_set_sclkout_div(struct snd_soc_dai *cpu_dai,
0039                     int div_id, int div)
0040 {
0041     struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(cpu_dai);
0042
0043     if (!div || (div & ~I2S_I2STIM_VALID_MASK))
0044         return -EINVAL;
0045
0046     drv_data->sysclk = 0;
0047
0048     writel(div, drv_data->base + I2S_I2STIM_OFFSET);
0049
0050     return 0;
0051 }
0052
0053 static int xlnx_i2s_set_sysclk(struct snd_soc_dai *dai,
0054                    int clk_id, unsigned int freq, int dir)
0055 {
0056     struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(dai);
0057
0058     drv_data->sysclk = freq;
0059     if (freq) {
0060         unsigned int bits_per_sample;
0061
0062         if (drv_data->is_32bit_lrclk)
0063             bits_per_sample = 32;
0064         else
0065             bits_per_sample = drv_data->data_width;
0066
0067         drv_data->ratnum.num = freq / (bits_per_sample * drv_data->channels) / 2;
0068         drv_data->ratnum.den_step = 1;
0069         drv_data->ratnum.den_min = 1;
0070         drv_data->ratnum.den_max = 255;
0071         drv_data->rate_constraints.rats = &drv_data->ratnum;
0072         drv_data->rate_constraints.nrats = 1;
0073     }
0074     return 0;
0075 }
0076
0077 static int xlnx_i2s_startup(struct snd_pcm_substream *substream,
0078                 struct snd_soc_dai *dai)
0079 {
0080     struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(dai);
0081
0082     if (drv_data->sysclk)
0083         return snd_pcm_hw_constraint_ratnums(substream->runtime, 0,
0084                              SNDRV_PCM_HW_PARAM_RATE,
0085                              &drv_data->rate_constraints);
0086
0087     return 0;
0088 }
0089
0090 static int xlnx_i2s_hw_params(struct snd_pcm_substream *substream,
0091                   struct snd_pcm_hw_params *params,
0092                   struct snd_soc_dai *i2s_dai)
0093 {
0094     u32 reg_off, chan_id;
0095     struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
0096
0097     if (drv_data->sysclk) {
0098         unsigned int bits_per_sample, sclk, sclk_div;
0099
0100         if (drv_data->is_32bit_lrclk)
0101             bits_per_sample = 32;
0102         else
0103             bits_per_sample = drv_data->data_width;
0104
0105         sclk = params_rate(params) * bits_per_sample * params_channels(params);
0106         sclk_div = drv_data->sysclk / sclk / 2;
0107
0108         if ((drv_data->sysclk % sclk != 0) ||
0109             !sclk_div || (sclk_div & ~I2S_I2STIM_VALID_MASK)) {
0110             dev_warn(i2s_dai->dev, "invalid SCLK divisor for sysclk %u and sclk %u\n",
0111                  drv_data->sysclk, sclk);
0112             return -EINVAL;
0113         }
0114         writel(sclk_div, drv_data->base + I2S_I2STIM_OFFSET);
0115     }
0116
0117     chan_id = params_channels(params) / 2;
0118
0119     while (chan_id > 0) {
0120         reg_off = I2S_CH0_OFFSET + ((chan_id - 1) * 4);
0121         writel(chan_id, drv_data->base + reg_off);
0122         chan_id--;
0123     }
0124
0125     return 0;
0126 }
0127
0128 static int xlnx_i2s_trigger(struct snd_pcm_substream *substream, int cmd,
0129                 struct snd_soc_dai *i2s_dai)
0130 {
0131     struct xlnx_i2s_drv_data *drv_data = snd_soc_dai_get_drvdata(i2s_dai);
0132
0133     switch (cmd) {
0134     case SNDRV_PCM_TRIGGER_START:
0135     case SNDRV_PCM_TRIGGER_RESUME:
0136     case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
0137         writel(I2S_CORE_CTRL_ENABLE, drv_data->base + I2S_CORE_CTRL_OFFSET);
0138         break;
0139     case SNDRV_PCM_TRIGGER_STOP:
0140     case SNDRV_PCM_TRIGGER_SUSPEND:
0141     case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
0142         writel(0, drv_data->base + I2S_CORE_CTRL_OFFSET);
0143         break;
0144     default:
0145         return -EINVAL;
0146     }
0147
0148     return 0;
0149 }
0150
0151 static const struct snd_soc_dai_ops xlnx_i2s_dai_ops = {
0152     .trigger = xlnx_i2s_trigger,
0153     .set_sysclk = xlnx_i2s_set_sysclk,
0154     .set_clkdiv = xlnx_i2s_set_sclkout_div,
0155     .startup = xlnx_i2s_startup,
0156     .hw_params = xlnx_i2s_hw_params
0157 };
0158
0159 static const struct snd_soc_component_driver xlnx_i2s_component = {
0160     .name = DRV_NAME,
0161     .legacy_dai_naming = 1,
0162 };
0163
0164 static const struct of_device_id xlnx_i2s_of_match[] = {
0165     { .compatible = "xlnx,i2s-transmitter-1.0", },
0166     { .compatible = "xlnx,i2s-receiver-1.0", },
0167     {},
0168 };
0169 MODULE_DEVICE_TABLE(of, xlnx_i2s_of_match);
0170
0171 static int xlnx_i2s_probe(struct platform_device *pdev)
0172 {
0173     struct xlnx_i2s_drv_data *drv_data;
0174     int ret;
0175     u32 format;
0176     struct device *dev = &pdev->dev;
0177     struct device_node *node = dev->of_node;
0178
0179     drv_data = devm_kzalloc(&pdev->dev, sizeof(*drv_data), GFP_KERNEL);
0180     if (!drv_data)
0181         return -ENOMEM;
0182
0183     drv_data->base = devm_platform_ioremap_resource(pdev, 0);
0184     if (IS_ERR(drv_data->base))
0185         return PTR_ERR(drv_data->base);
0186
0187     ret = of_property_read_u32(node, "xlnx,num-channels", &drv_data->channels);
0188     if (ret < 0) {
0189         dev_err(dev, "cannot get supported channels\n");
0190         return ret;
0191     }
0192     drv_data->channels *= 2;
0193
0194     ret = of_property_read_u32(node, "xlnx,dwidth", &drv_data->data_width);
0195     if (ret < 0) {
0196         dev_err(dev, "cannot get data width\n");
0197         return ret;
0198     }
0199     switch (drv_data->data_width) {
0200     case 16:
0201         format = SNDRV_PCM_FMTBIT_S16_LE;
0202         break;
0203     case 24:
0204         format = SNDRV_PCM_FMTBIT_S24_LE;
0205         break;
0206     default:
0207         return -EINVAL;
0208     }
0209
0210     if (of_device_is_compatible(node, "xlnx,i2s-transmitter-1.0")) {
0211         drv_data->dai_drv.name = "xlnx_i2s_playback";
0212         drv_data->dai_drv.playback.stream_name = "Playback";
0213         drv_data->dai_drv.playback.formats = format;
0214         drv_data->dai_drv.playback.channels_min = drv_data->channels;
0215         drv_data->dai_drv.playback.channels_max = drv_data->channels;
0216         drv_data->dai_drv.playback.rates    = SNDRV_PCM_RATE_8000_192000;
0217         drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
0218     } else if (of_device_is_compatible(node, "xlnx,i2s-receiver-1.0")) {
0219         drv_data->dai_drv.name = "xlnx_i2s_capture";
0220         drv_data->dai_drv.capture.stream_name = "Capture";
0221         drv_data->dai_drv.capture.formats = format;
0222         drv_data->dai_drv.capture.channels_min = drv_data->channels;
0223         drv_data->dai_drv.capture.channels_max = drv_data->channels;
0224         drv_data->dai_drv.capture.rates = SNDRV_PCM_RATE_8000_192000;
0225         drv_data->dai_drv.ops = &xlnx_i2s_dai_ops;
0226     } else {
0227         return -ENODEV;
0228     }
0229     drv_data->is_32bit_lrclk = readl(drv_data->base + I2S_CORE_CTRL_OFFSET) &
0230                    I2S_CORE_CTRL_32BIT_LRCLK;
0231
0232     dev_set_drvdata(&pdev->dev, drv_data);
0233
0234     ret = devm_snd_soc_register_component(&pdev->dev, &xlnx_i2s_component,
0235                           &drv_data->dai_drv, 1);
0236     if (ret) {
0237         dev_err(&pdev->dev, "i2s component registration failed\n");
0238         return ret;
0239     }
0240
0241     dev_info(&pdev->dev, "%s DAI registered\n", drv_data->dai_drv.name);
0242
0243     return ret;
0244 }
0245
0246 static struct platform_driver xlnx_i2s_aud_driver = {
0247     .driver = {
0248         .name = DRV_NAME,
0249         .of_match_table = xlnx_i2s_of_match,
0250     },
0251     .probe = xlnx_i2s_probe,
0252 };
0253
0254 module_platform_driver(xlnx_i2s_aud_driver);
0255
0256 MODULE_LICENSE("GPL v2");
0257 MODULE_AUTHOR("Praveen Vuppala  <praveenv@xilinx.com>");
0258 MODULE_AUTHOR("Maruthi Srinivas Bayyavarapu <maruthis@xilinx.com>");